Table 2: I/O Map - VersaLogic Viper Programmer's Reference Manual

System Resources and Maps
Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.

Table 2: I/O Map

I/O Address Range
2E8h – 2EFh
2F8h – 2FFh
3B0h – 3DFh
3E8h – 3EFh
3F8h – 3FFh
400h – 47Fh
500h – 5FFh
C80h – CBBh
CBCh – CBFh
CC0h – CCFh
3
Device/Owner
COM4 serial port default
COM2 serial port default
Legacy VGA registers
COM3 serial port default
COM1 serial port default
ACPI / Power management (reserved)
PCH GPIO (reserved)
EBX-38 FPGA Board Control Registers
EBX-38 FPGA 8254 Timer Registers
EBX-38 FPGA Additional Registers
VL-EBX-38 Programmer's Reference Manual