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AM64 GP EVM Series
Texas Instruments AM64 GP EVM Series Manuals
Manuals and User Guides for Texas Instruments AM64 GP EVM Series. We have
1
Texas Instruments AM64 GP EVM Series manual available for free PDF download: User Manual
Texas Instruments AM64 GP EVM Series User Manual (56 pages)
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 7 MB
Table of Contents
Table of Contents
1
1 Introduction
3
6 Revision History
4
2 Important Usage Notes
4
Power-On Usage Note
4
Figure 3-1. Top View of General Processor Board
4
Key Features
5
Figure 3-2. Bottom View of General Processor Board
5
Functional Block Diagram
7
Figure 3-3. General Processor Board Functional Block
7
Diagram
7
Power-On/Off Procedures
8
Power-On Procedure
8
Power-Off Procedure
9
Peripheral and Major Component Description
10
Clocking
10
Am64X Soc Clock
10
Ethernet PHY Clock
10
Figure 3-4. Am64X GP EVM Clock Tree
10
Pcie Clock
10
Table 3-1. Source Clock Selection for the Clock Buffer
10
Reset
11
Power
12
Current Monitoring
12
Power Input
12
Reverse Polarity Protection
12
Evm
12
Table 3-2. VMAIN LED
12
Table 3-3. INA Devices I2C Slave Address
12
Power Supply
13
Table 3-4. Power Test Points
13
Figure 3-6. Power Good Leds
14
Table 3-5. Power Leds
14
Figure 3-7. Power on and off Sequencing
15
Power Sequencing
15
Figure 3-8. Core Supply and Array Core Supply Options
16
Table 3-6. Soc Power Supply
16
Boot Modes
17
Configuration
17
Figure 3-10. Am64X GP EVP PCB, Boot Mode Selection Switches (SW2, SW3)
18
Figure 3-9. Am64X GP EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)
18
Table 3-7. BOOTMODE Bits
19
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]
19
Table 3-9. Boot Device Selection BOOTMODE[6:3]
19
Table 3-10. Primary Boot Media Configuration BOOTMODE[9:7]
20
Table 3-11. Backup Boot Mode Selection BOOTMODE[12:10]
20
Table 3-12. Backup Boot Media Configuration BOOTMODE
20
Jtag
21
Table 3-13. Selection of HSE Connector and JTAG TRACE Functionality
21
Table 3-14. TI20 Pin Connector (J25)
21
Figure 3-11. JTAG Interface
22
Table 3-15. TI 60-Pin Connector (J33) Pin-Out
22
Table 3-16. List of Signals Routed to Test Automation Header
23
Test Automation
23
Figure 3-12. Test Automation Header
24
Table 3-17. Test Automation Header (J38) Pin-Out
25
Figure 3-13. UART Interface
26
UART Interface
26
DDR4 Interface
27
Figure 3-14. DDR4 Interface
27
Memory Interfaces
27
Figure 3-15. Micro SD Interface
28
MMC Interface
28
Figure 3-16. Emmc Interface
29
OSPI Interface
29
Board ID EEPROM Interface
30
Figure 3-17. OSPI Interface
30
SPI EEPROM Interface
30
Table 3-18. Board ID Memory Header Information
30
Ethernet Interface
31
Figure 3-18. Ethernet Interface - CPSW Domain
31
Figure 3-19. Ethernet Interface - ICSSG Domain
32
DP83867 PHY Default Configuration
33
DP83869 PHY Default Configuration
33
Table 3-19. Default Strap Setting of CPSW Ethernet PHY
34
Table 3-20. Default Strap Setting of ICSSG Ethernet Phys
34
Figure 3-20. Ethernet Interface - CPSW Ethernet Strap
36
Figure 3-21. Ethernet Interface - ICSSG1 Ethernet Strap Settings
37
Figure 3-22. Ethernet Interface - ICSSG2 Ethernet Strap Settings
38
Ethernet Leds
39
Figure 3-23. GP Board Ethernet Interface - Leds
39
Display Interface
40
Table 3-21. Display Connector (J36) Pin-Out
40
Figure 3-24. USB 2.0 Host Interface
41
Pcie Interface
41
USB 2.0 Interface
41
Figure 3-25. Pcie Interface
42
Table 3-22. Pcie Jumper Options to Enable Root Complex and Endpoint Mode
42
Table 3-23. Pcie Connector (J27) Pin-Out
42
High Speed Expansion Interface
43
Table 3-24. Selection of PRG0 Signals on Application Connector
43
Figure 3-26. High Speed Expansion Connector
45
Figure 3-27. High Speed Expansion Connector Part 1
46
CAN Interface
47
Figure 3-28. High Speed Expansion Connector Part 2
47
Table 3-25. CAN (J31 and J32) Pin-Out
47
ADC Interface
48
Figure 3-29. CAN Interface
48
Interrupt
48
Table 3-26. ADC Connector (J3) Pin-Out
48
I2C Interface
49
Safety Connector
49
SPI Interface
49
Table 3-27. Safety Connector Pinouts
49
Table 3-28. I2C Test Header (J5) Pin-Out
49
Table 3-29. I2C Test Header (J4) Pin-Out
50
Figure 3-30. I2C Interfaces and Address Assignment to Its Peripherals
51
Figure 3-31. FSI Interface
52
FSI Interface
52
Table 3-30. FSI (J5) Connector Pin-Out
52
Soc Power
16
4 Known Issues and Modifications
53
Issue 1 - Embedded XDS110 Connection to Am64X Target in CCS
53
Figure 4-1. Am64X GP EVM Modification Label
53
Table 4-1. Am64X GP EVM Known Issues and Modifications
53
Figure 4-2. XDS110 CCS Connection Error Dialog
54
Figure 4-3. : XDS110 Debug Reset Utility Command-Line Function
54
Issue 2 - MDIO Ethernet PHY Communications
55
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