Phy Support Register (Supp - 0X5000 0018); Test Register (Test - 0X5000 001C); Mii Mgmt Configuration Register - NXP Semiconductors LPC1768 User Manual

NXP Semiconductors

11.7 PHY Support Register (SUPP - 0x5000 0018)

The PHY Support register (SUPP) has an address of 0x5000 0018. The SUPP register
provides additional control over the RMII interface. The bit definition of this register is
shown in
Table 114. PHY Support register (SUPP - address 0x5000 0018) bit description
Bit Symbol
7:0 -
8 SPEED
31:9 -
Unused bits in the PHY support register should be left as zeroes.

11.8 Test Register (TEST - 0x5000 001C)

The Test register (TEST) has an address of 0x5000 001C. The bit definition of this register
is shown in
Table 115. Test register (TEST - address 0x5000 ) bit description
Bit Symbol
0 SHORTCUT PAUSE
QUANTA
1 TEST PAUSE
2 TEST
BACKPRESSURE
31:3 -
11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020)
The MII Mgmt Configuration register (MCFG) has an address of 0x5000 0020. The bit
definition of this register is shown in
Table 116. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description
Bit Symbol
0 SCAN INCREMENT
1 SUPPRESS
PREAMBLE
5:2 CLOCK SELECT
UM10360_0
User manual
Table 10–114.
Function
Unused
This bit configures the Reduced MII logic for the current operating speed. When set,
100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
Unused
Table 10–115. These bits are used for testing purposes only.
Function
This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.
This bit causes the MAC Control sublayer to inhibit transmissions, just as if a
PAUSE Receive Control frame with a nonzero pause time parameter was received.
Setting this bit will cause the MAC to assert backpressure on the link. Backpressure
causes preamble to be transmitted, raising carrier sense. A transmit packet from the
system will be sent during backpressure.
Unused
Function
Set this bit to cause the MII Management hardware to perform read cycles across a
range of PHYs. When set, the MII Management hardware will perform read cycles
from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
continuous reads of the same PHY.
Set this bit to cause the MII Management hardware to perform read/write cycles
without the 32-bit preamble field. Clear this bit to cause normal cycles to be
performed. Some PHYs support suppressed preamble.
This field is used by the clock divide logic in creating the MII Management Clock
(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs
support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided
by the specified amount. Refer to
this field.
Rev. 00.06 — 5 June 2009
Chapter 10: LPC17xx Ethernet
Table 10–116.
Table 10–117 below for the definition of values for
UM10360
Reset
value
0x0
0
0x0
Reset
value
0
0
0
0x0
Reset
value
0
0
0
© NXP B.V. 2009. All rights reserved.
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