NXP Semiconductors LPC1754 Manuals

Manuals and User Guides for NXP Semiconductors LPC1754. We have 2 NXP Semiconductors LPC1754 manuals available for free PDF download: User Manual

NXP Semiconductors LPC1754 User Manual (841 pages)

ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 3 MB

Chapter 1: Lpc176X/5X Introductory Information

4
Introduction

4
Features

5
Applications

7
Ordering Information

8
- Part Options Summary
  8
Simplified Block Diagram

9
Chapter 35 : Supplementary Information

10
Architectural Overview

10
ARM Cortex-M3 Processor

10
- Cortex-M3 Configuration Options
  10
  - System Options
    10
  - Debug Related Options
    11
On-Chip Flash Memory System

11
On-Chip Static RAM

11
Block Diagram

12
Chapter 2: Lpc176X/5X Memory Map

13
Memory Map and Peripheral Addressing

13
Memory Maps

13
APB Peripheral Addresses

15
Memory Re-Mapping

16
- Boot ROM Re-Mapping
  16
AHB Arbitration

16
Bus Fault Exceptions

16
Chapter 3: Lpc176X/5X System Control

18
Introduction

18
Pin Description

18
Register Description

19
Reset

19
- Reset Source Identification Register (RSID - 0X400F C180)
  22
Brown-Out Detection

23
External Interrupt Inputs

24
- Register Description
  25
  - 0X400F C140
    25
  - 0X400F C148)
    26
  - 0X400F C14C)
    27
Other System Controls and Status Flags

29
- System Controls and Status Register (SCS - 0X400F C1A0)
  29
Chapter 4: Lpc176X/5X Clocking and Power Control

30
Summary of Clocking and Power Control Functions

30
Register Description

31
Oscillators

32
- Internal RC Oscillator
  32
- Main Oscillator
  32
- RTC Oscillator
  34
Clock Source Selection Multiplexer

35
- Clock Source Select Register (CLKSRCSEL - 0X400F C10C)
  35
PLL0 (Phase Locked Loop 0)

36
- PLL0 Operation
  36
- PLL0 and Startup/Boot Code Interaction
  36
- PLL0 Register Description
  37
- PLL0 Control Register (PLL0CON - 0X400F C080)
  37
- PLL0 Configuration Register (PLL0CFG - 0X400F C084)
  38
- PLL0 Status Register (PLL0STAT - 0X400F C088)
  39
- PLL0 Interrupt: PLOCK0
  40
- PLL0 Modes
  40
- PLL0 Feed Register (PLL0FEED - 0X400F C08C)
  41
- PLL0 and Power-Down Mode
  41
- PLL0 Frequency Calculation
  41
- Procedure for Determining PLL0 Settings
  43
- Examples of PLL0 Settings
  44
  - Example 1
    44
  - Example 2
    44
  - Example 3
    45
- PLL0 Setup Sequence
  47
PLL1 (Phase Locked Loop 1)

48
- PLL1 Register Description
  48
- PLL1 Control Register
  48
  - C0A0)
    49
- PLL1 Configuration Register (PLL1CFG - 0X400F C0A4)
  50
- PLL1 Status Register (PLL1STAT - 0X400F C0A8)
  50
- PLL1 Modes
  51
- PLL1 Interrupt: PLOCK1
  51
- PLL1 Feed Register
  52
  - C0Ac)
    52
- PLL1 and Power-Down Mode
  52
- PLL1 Frequency Calculation
  53
- Procedure for Determining PLL1 Settings
  53
Clock Dividers

55
Power Control

59
- Sleep Mode
  59
  - Deep Sleep Mode
    59
- Power-Down Mode
  60
- Deep Power-Down Mode
  61
- Peripheral Power Control
  61
- Register Description
  61
- Power Mode Control Register (PCON - 0X400F C0C0)
  62
- Encoding of Reduced Power Modes
  63
  - Wake-Up from Reduced Power Modes
    63
- Power Control for Peripherals Register (PCONP - 0X400F C0C4)
  63
- Power Control Usage Notes
  65
- Power Domains
  65
Wake-Up Timer

66
External Clock Output Pin

67
- Clock Output Configuration Register
  67
Chapter 5: Lpc176X/5X Flash Accelerator

69
Introduction

69
Flash Accelerator Blocks

69
- Flash Memory Bank
  69
- Flash Programming Issues
  70
Register Description

70
Flash Accelerator Configuration Register

71
Operation

71
Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (NVIC)

73
Features

73
Description

73
Interrupt Sources

73
Vector Table Remapping

76
- Examples
  76
Register Description

77
Chapter 7: Lpc176X/5X Pin Configuration

92
Lpc176X/5X Pin Configuration

92
Lpc176X/5X Pin Description

95
Chapter 8: Lpc176X/5X Pin Connect Block

105
How to Read this Chapter

105
Description

105
Pin Function Select Register Values

105
- Multiple Connections
  106
Pin Mode Select Register Values

106
- Function of PINMODE in Open Drain Mode
  107
Register Description

108
Chapter 9 : Lpc176X/5X General Purpose Input/Output (GPIO)

121
Basic Configuration

121
Features

121
- Digital I/O Ports
  121
- Interrupt Generating Digital Ports
  121
Applications

122
Pin Description

122
Register Description

123
GPIO Usage Notes

141
- Example: an Instantaneous Output of 0S and 1S on a GPIO Port
  141
- Writing to FIOSET/FIOCLR Vs. FIOPIN
  141
Chapter 10: Lpc176X/5X Ethernet

142
Basic Configuration

142
Introduction

142
Features

143
Architecture and Operation

144
DMA Engine Functions

145
Overview of DMA Operation

145
Ethernet Packet

146
Overview

147
- Partitioning
  147
- Example PHY Devices
  148
Pin Description

148
Registers and Software Interface

149
- Register Map
  149
Ethernet MAC Register Definitions

151
- MAC Configuration Register 1 (MAC1 - 0X5000 0000)
  151
- MAC Configuration Register 2 (MAC2 - 0X5000 0004)
  151
- Back-To-Back Inter-Packet-Gap Register (IPGT - 0X5000 0008)
  153
- Non Back-To-Back Inter-Packet-Gap Register (IPGR - 0X5000 000C)
  153
- Collision Window / Retry Register (CLRT - 0X5000 0010)
  154
- Maximum Frame Register (MAXF - 0X5000 0014)
  154
- PHY Support Register (SUPP - 0X5000 0018)
  154
- Test Register (TEST - 0X5000 001C)
  154
- MII Mgmt Configuration Register (MCFG - 0X5000 0020)
  155
- MII Mgmt Command Register
  156
  - 0X5000 0024)
    156
- MII Mgmt Address Register
  156
  - 0X5000 0028)
    156
- MII Mgmt Write Data Register
  156
  - 0X5000 002C)
    156
- MII Mgmt Read Data Register
  157
  - 0X5000 0030)
    157
- MII Mgmt Indicators Register
  157
- 0X5000 0034)
  157
  - Station Address 0 Register
    158
- Station Address 1 Register
  158
- Station Address 2 Register
  158
Control Register Definitions

159
Receive Filter Register Definitions

167
Module Control Register Definitions

169
- Interrupt Status Register
  169
  - 0X5000 0FE0)
    169
- Interrupt Enable Register
  170
  - 0X5000 0FE4)
    170
  - 0Fe8)
    170
- Interrupt Set Register (Intset - 0X5000 0FEC)
  171
- Power-Down Register
  172
  - 0X5000 0FF4)
    172
Descriptor and Status Formats

173
- Receive Descriptors and Statuses
  173
- Transmit Descriptors and Statuses
  176
Ethernet Block Functional Description

178
- Overview
  178
- AHB Interface
  179
Interrupts

179
- Direct Memory Access (DMA)
  179
- Initialization
  182
- Transmit Process
  183
- Receive Process
  189
- Transmission Retry
  195
- Status Hash CRC Calculations
  195
- Duplex Modes
  196
- IEE 802.3/Clause 31 Flow Control
  196
- Half-Duplex Mode Backpressure
  198
- Receive Filtering
  199
- Power Management
  201
- Wake-Up on LAN
  201
- Enabling and Disabling Receive and Transmit
  203
- Transmission Padding and CRC
  205
- Huge Frames and Frame Length Checking
  206
- Statistics Counters
  206
- MAC Status Vectors
  206
- Reset
  207
- Ethernet Errors
  208
AHB Bandwidth

209
- DMA Access
  209
- Types of CPU Access
  210
- Overall Bandwidth
  210
CRC Calculation

212
Chapter 11 : Lpc176X/5X USB Device Controller

214
How to Read this Chapter

214
Basic Configuration

214
Introduction

214
Features

215
Fixed Endpoint Configuration

215
Functional Description

216
- Analog Transceiver
  217
- Serial Interface Engine (SIE)
  217
- Endpoint RAM (EP_RAM)
  217
- EP_RAM Access Control
  217
- DMA Engine and Bus Master Interface
  218
- Register Interface
  218
- Softconnect
  218
- Goodlink
  218
Operational Overview

218
Pin Description

219
Clocking and Power Management

219
- Power Requirements
  219
- Clocks
  219
- Power Management Support
  220
- Remote Wake-Up
  221
Register Description

221
Interrupt Handling

242
- Slave Mode
  243
- DMA Mode
  243
Serial Interface Engine Command Description

245
USB Device Controller Initialization

253
Slave Mode Operation

254
- Interrupt Generation
  254
- Data Transfer for out Endpoints
  255
- Data Transfer for in Endpoints
  255
DMA Operation

255
- Transfer Terminology
  256
- USB Device Communication Area
  256
- Triggering the DMA Engine
  257
- The DMA Descriptor
  257
- Next_Dd_Pointer
  258
- Dma_Mode
  258
- Next_Dd_Valid
  258
- Isochronous_Endpoint
  259
- Max_Packet_Size
  259
- Dma_Buffer_Length
  259
- Dma_Buffer_Start_Addr
  259
- Dd_Retired
  259
- Dd_Status
  259
- Packet_Valid
  260
- Ls_Byte_Extracted
  260
- Ms_Byte_Extracted
  260
- Present_Dma_Count
  260
- Message_Length_Position
  260
- Isochronous_Packetsize_Memory_Address
  260
- Non-Isochronous Endpoint Operation
  260
- Setting up DMA Transfers
  260
- Finding DMA Descriptor
  261
- Transferring the Data
  261
- Optimizing Descriptor Fetch
  261
- Ending the Packet Transfer
  261
- No_Packet DD
  262
- Isochronous Endpoint Operation
  262
- Setting up DMA Transfers
  262
- Finding the DMA Descriptor
  262
- Transferring the Data
  263
  - OUT Endpoints
    263
  - IN Endpoints
    263
- DMA Descriptor Completion
  263
- Isochronous out Endpoint Operation
  263
  - Example
    263
- Auto Length Transfer Extraction (ATLE) Mode Operation
  264
  - OUT Transfers in ATLE Mode
    265
  - IN Transfers in ATLE Mode
    266
- Setting up the DMA Transfer
  266
- Finding the DMA Descriptor
  266
- Transferring the Data
  266
  - OUT Endpoints
    266
  - IN Endpoints
    266
- Ending the Packet Transfer
  267
  - OUT Endpoints
    267
  - IN Endpoints
    267
Double Buffered Endpoint Operation

267
- Bulk Endpoints
  267
- Isochronous Endpoints
  269
Chapter 12 : Lpc176X/5X USB Host Controller

270
How to Read this Chapter

270
Basic Configuration

270
Introduction

270
- Features
  271
- Architecture
  271
Interfaces

271
- Pin Description
  272
- USB Host Usage Note
  272
- Software Interface
  272
- Register Map
  272
- USB Host Register Definitions
  273
Chapter 13: Lpc176X/5X USB OTG

274
How to Read this Chapter

274
Basic Configuration

274
Introduction

274
Features

274
Architecture

275
Modes of Operation

275
Pin Configuration

276
Register Description

278
USB Interrupt Status Register

278
HNP Support

287
- B-Device: Peripheral to Host Switching
  288
  - Remove D+ Pull-Up
    290
  - Add D+ Pull-Up
    291
- A-Device: Host to Peripheral HNP Switching
  291
  - Ceiver
    294
  - Discharge VBUS
    294
  - Load and Enable OTG Timer
    295
  - Stop OTG Timer
    295
  - Suspend Host on Port 1
    295

NXP Semiconductors LPC1754 User Manual (808 pages)

Brand: NXP Semiconductors | Category: Controller | Size: 4 MB

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

More NXP Semiconductors Manuals

NXP Semiconductors LPC1754 Manuals

NXP Semiconductors LPC1754 User Manual (841 pages)

Table of Contents

Chapter 1: Lpc176X/5X Introductory Information

Introduction

Features

Applications

Ordering Information

Simplified Block Diagram

Chapter 35 : Supplementary Information

Architectural Overview

ARM Cortex-M3 Processor

On-Chip Flash Memory System

On-Chip Static RAM

Block Diagram

Chapter 2: Lpc176X/5X Memory Map

Memory Map and Peripheral Addressing

Memory Maps

APB Peripheral Addresses

Memory Re-Mapping

AHB Arbitration

Bus Fault Exceptions

Chapter 3: Lpc176X/5X System Control

Introduction

Pin Description

Register Description

Reset

Brown-Out Detection

External Interrupt Inputs

Other System Controls and Status Flags

Chapter 4: Lpc176X/5X Clocking and Power Control

Summary of Clocking and Power Control Functions

Register Description

Oscillators

Clock Source Selection Multiplexer

PLL0 (Phase Locked Loop 0)

PLL1 (Phase Locked Loop 1)

Clock Dividers

Power Control

Wake-Up Timer

External Clock Output Pin

Chapter 5: Lpc176X/5X Flash Accelerator

Introduction

Flash Accelerator Blocks

Register Description

Flash Accelerator Configuration Register

Operation

Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (NVIC)

Features

Description

Interrupt Sources

Vector Table Remapping

Register Description

Chapter 7: Lpc176X/5X Pin Configuration

Lpc176X/5X Pin Configuration

Lpc176X/5X Pin Description

Chapter 8: Lpc176X/5X Pin Connect Block

How to Read this Chapter

Description

Pin Function Select Register Values

Pin Mode Select Register Values

Register Description

Chapter 9 : Lpc176X/5X General Purpose Input/Output (GPIO)

Basic Configuration

Features

Applications

Pin Description

Register Description

GPIO Usage Notes

Chapter 10: Lpc176X/5X Ethernet

Basic Configuration

Introduction

Features

Architecture and Operation

DMA Engine Functions

Overview of DMA Operation

Ethernet Packet

Overview

Pin Description

Registers and Software Interface