Analog Transceiver; Serial Interface Engine (Sie); Endpoint Ram (Ep_Ram); Ep_Ram Access Control - NXP Semiconductors LPC1768 User Manual

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NXP Semiconductors

DMA interface

(AHB master)

Fig 25. USB device controller block diagram

6.1 Analog transceiver

The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX

sends/receives the bi-directional D+ and D- signals of the USB bus.

The SIE implements the full USB protocol layer. It is completely hardwired for speed and

needs no firmware intervention. It handles transfer of data between the endpoint buffers in

EP_RAM and the USB bus. The functions of this block include: synchronization pattern

recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,

PID verification/generation, address recognition, and handshake evaluation/generation.

Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for

this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the

EP_RAM. The total EP_RAM space required depends on the number of realized

endpoints, the maximum packet size of the endpoint, and whether the endpoint supports

double buffering.

The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the

three sources that can access it: the CPU (via the Register Interface), the SIE, and the

Rev. 00.06 — 5 June 2009

Chapter 11: LPC17xx USB device controller

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