Bc Board - Sony BVM-D32E1WA Maintenance Manual

6-3. BC Board

1. Outline
The BC board controls the entire system with the system control CPU. The BC board has the function of
communication with external equipment, communication with system controller, generation of internal
signal, creation of safe area display, generation of H. sync and V. sync signal for deflection circuit and the
on-screen display function.
2. CPU operation block
IC1 is the system control CPU that controls the entire system. IC3 is the ROM that stores the system
control software. IC4 is the SRAM that stores the adjustment data such as picture size. Because the
memory contents of the SRAM is cleared when the main power is turned, it is backed up by the back
battery (BAT1). When the backup battery is going to be replaced, the data contents are not cleared if the
BAT1 is replaced within five minutes. IC7 is the EEP-ROM in which the model data (such as model
name, etc.,) is stored. The data in the EEP-ROM is kept stored even when the main power is turned off.
Communication with the sub-CPUs on the other boards is performed by the MIS0, MOSI, SCLK and
SLOT0 to SLOT7 signals. The counter-part of communication is selected by the SLOT0 to SLOT7
signals.
3. Communication with the control block (BKM-10R)>
The communication with the control block (BKM-10R) is performed by the RS-422 transceiver (IC14).
The data such as key input data, LED turning-on data and memory card data are communicated.
4. Communication with BKM-11R
The communication with the control block (BKM-11R) is performed by the RS-232 transceiver (IC36).
5. Remote circuit, ISR circuit
The remote control using the serial communication is performed by the RS-485 transceiver (IC25, IC26).
The ISR is performed by the RS-232 transceiver (IC36). The parallel remote (REMOTE2) is inputted to
IC1 through the buffer (IC550, IC551) and I/O expander (IC5).
6. PLD (IC803) circuit
IC803 is a PLD. It is used as the configuration by the configuration ROM (IC890). The fundamental
clock signal is the clock signal that is outputted from PLL IC (IC800). When the internal signal is going
to be outputted, the 27 MHz clock that is generated by IC822 is used as the fundamental clock signal.
The clock signal for communication is generated by PLD. The clock signal that is outputted from IC809
pin-2 is frequency-divided inside the PLD. The clock signal that is generated by dividing the clock
frequency, becomes the fundamental clock signal for IC22, IC23 and IC24.
The PLD generates the H. sync (BC HS out) and the V. sync (BC VS out) signals that are used as the
reference for deflection circuit inside the PLD. At the same time, generation of the H. delay and V. delay
timing signals, and phase adjustment to shift the H. sync to the front in the case of the 1080/481 signals.
The safe area display is generated by the PLD. The SAD output and the on-screen display (OSD) are
inputted to the OR-gate circuit. Output of the OR-gate is supplied to external circuits.
The internal signals are generated from the 27 MHz clock. Data of the internal signals is stored in the
video RAM (IC804). The video RAM data is supplied from the CPU.
The sample pulse that is used for automatic chroma phase adjustment, is also created here.
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BVM-D32E1WA/D32E1WE/D32E1WU