Sony BVM-D32E1WA Maintenance Manual page 103

2. Vertical system
. V DELAY circuit
IC2002 generates the positive polarity pulse using the fall-down edge of the V. sync that is supplied from
the BC board as the trigger signal. This positive polarity pulse is inputted to IC2001. However, because
polarity of the V. sync signal is inverted by IC1002 during the V. DELAY mode, the positive polarity
pulse is delayed by about 1/2 of the vertical period i.e., the V. sync pulse width.
. V OSC circuit
IC2001 generates the sawtooth wave V. DRIVE signal of the vertical cycle as it oscillates in synchronism
with the positive polarity pulse that is supplied from the V DELAY circuit.
The V. DRIVE signal has the vertical picture size (V SIZE) adjustment function, the vertical picture
position (V CENTER) adjustment function and the vertical linearity balance (V LIN BAL) correction
function.
. Vertical deflection circuit
The V. DRIVE signal and the V. CENT signal that are outputted from IC2001 are inputted to IC601 to
drive the V. DY.
3. Other output circuits
. Rotation circuit
The rotation voltage that is outputted from IC7005 is sent to IC401 that controls the current flowing
through the rotation coil of the DY.
. Landing circuit
The landing voltage that is outputted from IC7005 is sent to IC801 that controls the current flowing
through the landing correction coil.
. H. STAT circuit
The H. STAT voltage that is outputted from IC7005 is sent to IC801 so that the current flowing through
the H. STAT coil of the DY is controlled.
. V convergence circuit
The V. CONV signal that is outputted from IC204 of the D board is amplified by IC801 that drives NTC
or the V. STAT coil of DY.
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BVM-D32E1WA/D32E1WE/D32E1WU