Asynchronous Interface
Figure 1−10. Asynchronous Write Timing Diagram
Setup
2
†
Clock
‡
CE
§
CE
BE[3:0]
EA[21:2]
Á Á
¶
ED[31:0]
Á Á
AOE
ARE
AWE
ARDY
†
Clock = CLKOUT1 for C620x/C670x DSP.
= ECLKOUT for C621x/C671x DSP.
= ECLKOUT1 for C64x DSP.
‡
CE waveform for C620x/C670x DSP.
§
CE waveform for C621x/C671x DSP and C64x DSP.
¶
For C621x/C671x EMIF, ED may become valid one cycle later (see section 1.5.3.1).
1-22
Overview
Hold
Strobe
Setup
3
1
2
BE1
A1
D1
Strobe
Hold
CE write hold
3
1
BE2
A2
Á Á
D2
Á Á
3
SPRU266A