Spy-Bi-Wire (Sbw) Timing And Control; Timing Diagram (Alternative Timing) - Texas Instruments MSP430 User Manual

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8.2.2.2 Macros for Spy-Bi-Wire (SBW) Interface
All JTAG macros described in
software source along with this document.

8.2.3 Spy-Bi-Wire (SBW) Timing and Control

The following sections provide a basic understanding of the SBW implementation as it relates to
supporting generation of the macro function timing signals. This is intended to enable development of
custom MSP430 programming solutions, rather than just relying on the example application code also
provided.
8.2.3.1 Basic Timing
The SBW interface serial communication uses time-division multiplexing, allocating three time slots:
TMS_SLOT, TDI_SLOT, and TDO_SLOT. In order to clock TCLK via the SBW interface in a similar
method as it is clocked via TDI during 4-wire JTAG access, an alternative JTAG timing method is
implemented. This implementation makes use of the fact that the TDI and TMS signals are clocked into
the TAP controller or shift register with the rising edge of TCK as shown in
SBWTCK
TCK
The implemented logic used to translate between the 2-wire and 4-wire interfaces is shown in
SLAU265 – February 2009
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Section 8.2.2.1 also apply to the 2-wire interface and are provided as
TMS and TDI
clocked into TAP
shift register
TMS Slot TDI Slot
Figure 8-7. Timing Diagram (Alternative Timing)
Figure
7 s
< m
TDO Slot
MSP430 Programming Via the JTAG Interface
Interface and Instructions
8-7.
Figure 8-8.
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