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2
SPI Operation Modes
Figure 1.
SPI Module Block Diagram (Five Pin Mode Shown)
SPIEMU
16
SPIBUF
16
16 bit shift register
SPIDAT1
/
SPIDAT0
Charlen
SPICTRL1.4:0
ICLK from System
The SPI operates in a master or slave mode. The MASTER bit (SPICTRL2.3)
selects the configuration of the SPISIMO and SPISOMI pins and the
CLKMOD bit (SPICTRL2.5) determines whether an internal or external clock
source will be used.
The slave chip select (SPISCS) pin is used when communicating with
multiple slave devices. When the master (SPI sending out the clock stream)
writes to SPIDAT1, the SPISCS pin is automatically driven low to select the
slave connected to that signal. Writing to SPIDAT0 will not drive SPISCS low,
thus allowing the master to communicate with all slave devices connected to
the same SPI bus.
In addition, a handshaking mechanism, provided by the SPIENA pin, enables
the slave to delay the generation of the clock signal supplied by the master
as long as it is not prepared for the next exchange of data.
RCVR
SPICTRL2.2
RXINT
SPICTRL2.0
Master
SPICTRL2.3
Clock polarity
SPICTRL2.1
PRESCALE
SPICTRL1.12:5
Serial Peripheral Interface (SPI) Module (SPNU195E)
SPI Operation Modes
OVRN INT EN
SPICTRL2.3
RXINT
SPICTRL2.1
Clock
SPICTRL2.0
CLKMOD
SPICTRL2.5
to CIM
SPISOMI
SPISIMO
SPISCS
SPIENA
SPICLK
3
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