Variable Chip Select Setup And Hold Timing (Master Only) - Texas Instruments TMS470R1x Reference Manual

MibSPI Operation Modes
2.13

Variable Chip Select Setup and Hold Timing (Master only)

In order to support slow slave devices, a 5-bit delay counter can be
configured to delay the data transmission after the chip select is activated. A
second 5-bit delay counter can be configured to delay the chip select
deactivation after the last data bit transfer. Both delay counters are clocked
with ICLK (see section 7.17).
Note:
If the CSHOLD bit is set within the control field, the current hold time and the
following set-up time will not be applied in between transactions.
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