Emif To Zero Bus Turnaround (Zbt) Sram Interface Block Diagram - Texas Instruments TMS320C6000 DSP Reference Manual

Programmable Synchronous Interface
4.5.2 Zero Bus Turnaround (ZBT) SRAM Interface
Figure 4−14. EMIF to Zero Bus Turnaround (ZBT) SRAM Interface Block Diagram
4-28 TMS320C64x EMIF
The programmable synchronous mode supports zero bus turnaround (ZBT)
SRAM interface shown in Figure 4−14. For ZBT SRAM interface, the following
fields in CESEC must be set:
SYNCRL = 10b; 2 cycle read latency
-
SYNCWL = 10b; 2 cycle write latency
-
CEEXT = 0; CE goes inactive after the final command has been issued
-
RENEN = 0; SADS/SRE signal acts as SADS signal.
-
ECLKIN
ECLKOUTn
SADS/SRE
External
memory
interface
(EMIF)
BE[7:0]
EA[all]
ED[63:0]
†
ECLKOUTn used is selected by the SNCCLK bit in the CESECn register.
‡
The MTYPE field selects the interface to be 8-, 16-, 32-, or 64-bits wide.
For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used.
For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used.
External
clock
†
CEn
SOE
SWE
‡
‡
‡
CLK
CE
ADV/LD
ZBT
OE
SRAM
R/W
BE[7:0]
A[N:0]
D[63:0]
SPRU266A