Sbsram Six-Word Read Timing Diagram; Sbsram In Linear Burst Mode - Texas Instruments TMS320C6000 DSP Reference Manual

SBSRAM Interface
Table 3−8. BSRAM in Linear Burst Mode
S
3.5.1 SBSRAM Read
Figure 3−12. SBSRAM Six-Word Read Timing Diagram
ECLKOUT
CE
BE[3:0]
EA[21:2]
†
ED[31:0]
SSADS
SSOE
SSWE
†
ED[31:16] do not apply to C6712/C6712C DSP.
3-22 TMS320C621x/C671x EMIF
SBSRAM address
EMIF address
First address
Fourth address
Figure 3−12 shows
C621x/C671x EMIF. The address starts with EA[4:2] equal to 010b. The EMIF
strobes a new address into the SBSRAM on the third cycle to prevent the
internal burst counter from rolling over to 000b. The burst is terminated by
deasserting the CEn signal while SSADS is strobed low.
Read/D1
Read
latched
BE1 BE2 BE3
EA[4:2]=010b
Á Á
D1
Case 1 Case 2
A[1:0] A[1:0]
EA[3:2] EA[3:2]
00
01
10
11
a six-word read
D2 D3 D4
latched latched latched latched latched
BE4 BE5 BE6
EA[4:2]=100b
D2 D3 D4
Case 3
A[1:0]
EA[3:2]
01 10
10 11
11 00
00 01
of an SBSRAM
D5 D6
latched latched/deselect
Á Á
D5 D6
SPRU266A
Case 4
A[1:0]
EA[3:2]
11
00
01
10
for the