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Epson E0C6001 Technical Manual

Cmos 4-bit single chip microcomputer
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MF943-02
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
E0C6001 T
M
ECHNICAL
ANUAL
E0C6001 Technical Hardware
E0C6001 Technical Software

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  Summary of Contents for Epson E0C6001

  • Page 1 MF943-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER E0C6001 T ECHNICAL ANUAL E0C6001 Technical Hardware E0C6001 Technical Software...
  • Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products.
  • Page 3 This manual is individualy described about the hardware and the software of the E0C6001. I. E0C6001 Technical Hardware This part explains the function of the E0C6001, the circuit configura- tions, and details the controlling method. II. E0C6001 Technical Software This part explains the programming method of the E0C6001.
  • Page 4 E0C6001 Technical Hardware...
  • Page 5: Table Of Contents

    CONTENTS CHAPTER 1 INTRODUCTION ............... Configuration ..............Features ................Block Diagram ..............Pin Layout Diagram ............Pin Description ..............CHAPTER 2 POWER SUPPLY AND INITIAL RESET ........ Power Supply ..............Initial Reset ..............Oscillation detection circuit ........I-9 Reset pin (RESET) ............ I-9 Simultaneous high input to input ports (K00–K03) ...
  • Page 6 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...... I-13 Memory Map ..............I-13 Oscillation Circuit ............I-18 Crystal oscillation circuit ......... I-18 CR oscillation circuit ..........I-19 Input Port (K00–K03) ............I-20 Configuration of input port ........I-20 Interrupt function ........... I-20 Mask option ............
  • Page 7 Interrupt and HALT ............I-51 Interrupt factors ............I-53 Specific masks and factor flags for interrupt .... I-54 Interrupt vectors ............. I-54 Control of interrupt ..........I-55 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ......I-56 CHAPTER 6 ELECTRICAL CHARACTERISTICS ........I-58 Absolute Maximum Rating ..........
  • Page 8: Chapter 1 Introduction

    (R00, R01), one 4-bit I/O port (P00– P03) and one timer (clock timer). Because of their low voltage operation and low power con- sumption, the E0C6001 Series are ideal for a wide range of applications. Configuration The E0C6001 Series are configured as follows, depending on the supply voltage.
  • Page 9: Features

    E0C6001 TECHNICAL HARDWARE Features Built-in oscillation circuit Crystal or CR oscillation circuit, 32.768 kHz (typ.) Instruction set 100 instructions 1,024 words ×12 bits ROM capacity 80 words × 4 bits RAM capacity (data RAM) Input port 4 bits (Supplementary pull-down resistors may be used )
  • Page 10: Block Diagram

    CHAPTER 1: INTRODUCTION Block Diagram System Reset 1,024 × 12 Control Core CPU E0C6200B Interrupt × Generator COM0 K00~K03 I Port COM3 SEG0 Driver Test Port TEST SEG19 I/O Port P00~P03 Power Controller O Port R00, R01 FOUT (FOUT/BUZZER) & Timer BUZZER (BUZZER)
  • Page 11: Pin Layout Diagram

    E0C6001 TECHNICAL HARDWARE Pin Layout Diagram QFP12-48pin INDEX Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name OSC2 TEST COM0 RESET COM1 N.C. SEG19 SEG9 COM2 SEG18 SEG8 COM3 SEG17 SEG7 SEG16 SEG6...
  • Page 12: Pin Description

    CHAPTER 1: INTRODUCTION Pin Description Table 1.5.1 Pin description Terminal Name Pin No. Input/Output Function Power source (+) terminal Power source (-) terminal Oscillation and internal logic system regulated voltage output terminal × 1/2) LCD system reducer output terminal (V ×...
  • Page 13: Chapter 2 Power Supply And Initial Reset

    (<V or V > for LCDs). When the E0C6001 LCD power is selected for 4.5 V LCD panel by mask option, the E0C6001 short-circuits between <V > and <V > in internally, and the voltage booster/ reducer generates <V...
  • Page 14 CHAPTER 2: POWER SUPPLY AND INITIAL RESET • E0C6001 4.5 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias Note: V is shorted to V inside the IC. 3 V LCD panel 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias...
  • Page 15: Initial Reset

    E0C6001 TECHNICAL HARDWARE Initial Reset To initialize the E0C6001 Series circuits, an initial reset must be executed. There are three ways of doing this. (1) Initial reset by the oscillation detection circuit (Note) (2) External initial reset via the RESET pin (3) External initial reset by simultaneous high input to pins K00–K03 (depending on mask option)
  • Page 16: Oscillation Detection Circuit

    CHAPTER 2: POWER SUPPLY AND INITIAL RESET The oscillation detection circuit outputs the initial reset Oscillation detection signal at power-on until the crystal oscillation circuit starts circuit oscillating, or when the crystal oscillation circuit stops oscillating for some reason. However, use the following reset functions at power-on because the initial reset function by the oscillation detection circuit may not operate normally depending on the power-on procedure.
  • Page 17: Internal Register Following Initialization

    E0C6001 TECHNICAL HARDWARE An initial reset initializes the CPU as shown in the table Internal register fol- below. lowing initialization Table 2.2.2 CPU Core Initial values Name Signal Number of Bits Setting Value Program counter step Program counter page New page pointer...
  • Page 18: Chapter 3 Cpu, Rom, Ram

    E0C6200B. Refer to the "E0C6200/6200A Core CPU Manual" for details of the E0C6200B. Note the following points with regard to the E0C6001 Series: (1) The SLEEP operation is not provided, so the SLP instruc- tion cannot be used.
  • Page 19: Rom

    E0C6001 TECHNICAL HARDWARE 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 1,024 × 12-bit steps. The program area is 4 pages (0–3), each consisting of 256 steps (00H–FFH). After an initial reset, the program start address is page 1, step 00H.
  • Page 20: Chapter 4 Peripheral Circuits And Operation

    CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the E0C6001 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the pe- ripheral circuits operate.
  • Page 21 E0C6001 TECHNICAL HARDWARE Table 4.1.1(a) I/O memory map Register Address Comment Name High – High – 0E0H Input port (K00–K03) High – – High High – Timer data (clock timer 2 Hz) High – Timer data (clock timer 4 Hz) 0E4H –...
  • Page 22 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map Register Address Comment Name 0EDH Interrupt factor flag (K00–K03) IT32 Interrupt factor flag (clock timer 2 Hz) 0EFH Interrupt factor flag (clock timer 8 Hz) IT32 Interrupt factor flag (clock timer 32 Hz) BUZZER FOUT High...
  • Page 23 E0C6001 TECHNICAL HARDWARE Table 4.1.1(c) I/O memory map Register Address Comment Name TMRST TMRST Reset – Reset Clock timer reset 0F9H HLMOD HLMOD Heavy Normal Heavy load protection mode register load load 0FAH CSDC Static Dynamic LCD drive switch CSDC...
  • Page 24 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(d) I/O memory map Register Address Comment Name XBZR XFOUT1 XFOUT0 XBZR 2 kHz 4 kHz Buzzer frequency control 0FDH High XFOUT1 FOUT frequency control: XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT1(1), XFOUT0(0) ->...
  • Page 25: Oscillation Circuit

    E0C6001 TECHNICAL HARDWARE Oscillation Circuit Crystal oscillation The E0C6001 Series have a built-in crystal oscillation circuit. This circuit generates the operating clock for the circuit CPU and peripheral circuit on connection to an external crystal oscillator (typ. 32.768 kHz) and trimmer capacitor (5–25 pF).
  • Page 26: Cr Oscillation Circuit

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) For the E0C6001 Series, CR oscillation circuit (typ. 65 kHz) CR oscillation circuit may also be selected by a mask option. Figure 4.2.2 is the block diagram of the CR oscillation circuit.
  • Page 27: Input Port (K00-K03

    E0C6001 TECHNICAL HARDWARE Input Port (K00–K03) Configuration of The E0C6001 Series have a 4-bit general-purpose input port. Each of the input port pins (K00–K03) has an internal input port pull-down resistance. The pull-down resistance can be selected for each bit with the mask option.
  • Page 28 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Port) One for each pin series Address Noise Interrupt Interrupt factor rejector flag (IK) request Address Fig. 4.3.2 Mask option Interrupt mask (K00–K03) register (EIK) Input interrupt circuit configuration Address (K00–K03) The interrupt mask registers (EIK00–EIK03) enable the interrupt mask to be selected individually for K00–K03.
  • Page 29: Mask Option

    E0C6001 TECHNICAL HARDWARE Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clear- ing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status).
  • Page 30: Control Of Input Port

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Port) Table 4.3.1 list the input port control bits and their ad- Control of input port dresses. Table 4.3.1 Input port control bits Register Address Comment Name High – High – 0E0H Input port (K00–K03) High –...
  • Page 31 E0C6001 TECHNICAL HARDWARE EIK00–EIK03 Interrupt mask registers (0E8H) Masking the interrupt of the input port pins can be done with these registers. When 1 is written: Enable When 0 is written: Mask Reading: Valid With these registers, masking of the input port bits can be done for each of the four bits.
  • Page 32: Output Port (R00, R01

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Port) Output Port (R00, R01) Configuration of The E0C6001 Series have a 2-bit general output port (R00, R01). output port Output specification of the output port can be selected in a bit unit with the mask option. Two kinds of output specifi- cations are available: complementary output and Pch open drain output.
  • Page 33: Mask Option

    E0C6001 TECHNICAL HARDWARE The mask option enables the following output port selection. Mask option (1) Output specification of output port The output specifications for the output port (R00, R01) may be either complementary output or Pch open drain output for each of the two bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port.
  • Page 34 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Port) FOUT (R00) When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock frequency) or clock frequency divided into fosc. Clock frequency may be se- lected individually for F1–F4, from among 5 types by mask option;...
  • Page 35: Control Of Output Port

    E0C6001 TECHNICAL HARDWARE Control of output Table 4.4.3 lists the output port control bits and their ad- dresses. port Table 4.4.3 Control bits of output port Register Address Comment Name BUZZER FOUT High R01 output port data 0F3H BUZZER Buzzer ON/OFF control register...
  • Page 36 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Port) R00 (when FOUT is Special output port data (0F3H D0) selected) Controls the FOUT (clock) output. When 1 is written: Clock output When 0 is written: Low level (DC) output Reading: Valid FOUT output can be controlled by writing data to R00.
  • Page 37 E0C6001 TECHNICAL HARDWARE R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1) and BUZZER is Controls the buzzer output. selected) When 1 is written: Buzzer output When 0 is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01.
  • Page 38: I/O Port (P00-P03

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Port) I/O Port (P00–P03) Configuration of I/O The E0C6001 Series have a 4-bit general-purpose I/O port. Figure 4.5.1 shows the configuration of the I/O port. The port four bits of the I/O port P00–P03 can be set to either input mode or output mode.
  • Page 39: I/O Control Register And I/O Mode

    E0C6001 TECHNICAL HARDWARE Input or output mode can be set for the four bits of I/O port I/O control register P00–P03 by writing data into I/O control register IOC. and I/O mode To set the input mode, 0 is written to the I/O control regis- ter.
  • Page 40: Control Of I/O Port

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Port) Table 4.5.1 lists the I/O port control bits and their ad- Control of I/O port dresses. Table 4.5.1 I/O port control bits Register Address Comment Name – High High – 0F6H I/O port (P00–P03) –...
  • Page 41 E0C6001 TECHNICAL HARDWARE The pin voltage level of the I/O port is read. When the I/ O port is in the input mode the voltage level being input to the port pin can be read; in the output mode the output voltage level can be read.
  • Page 42: Lcd Driver (Com0-Com3, Seg0-Seg19

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD Driver (COM0–COM3, SEG0–SEG19) The E0C6001 Series have four common pins and 20 (SEG0– Configuration of LCD SEG19) segment pins, so that an LCD with a maximum of driver 80 (20 × 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally.
  • Page 43 E0C6001 TECHNICAL HARDWARE LCD lighting status COM0 COM0 COM1 COM2 COM3 COM1 SEG0–19 COM2 Not lit COM3 0–19 Fig. 4.6.1 Frame frequency Drive waveform for 1/4 duty (1/3 bias) I-36...
  • Page 44 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 LCD lighting status COM0 COM1 COM1 COM2 SEG0–19 COM2 Not lit COM3 0–19 Fig. 4.6.2 Frame frequency Drive waveform for 1/3 duty (1/3 bias) I-37...
  • Page 45 E0C6001 TECHNICAL HARDWARE LCD lighting status COM0 COM0 COM1 SEG0–19 COM1 Not lit COM2 COM3 0–19 Fig. 4.6.3 Frame frequency Drive waveform for 1/2 duty (1/3 bias) I-38...
  • Page 46 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD lighting status COM0 COM0 L1, L2 COM1 COM2 COM1 COM3 SEG0–19 COM2 Not lit COM3 L1, L2 0–19 Fig. 4.6.4 Frame frequency Drive waveform for 1/4 duty (1/2 bias) I-39...
  • Page 47 E0C6001 TECHNICAL HARDWARE LCD lighting status COM0 COM0 L1, L2 COM1 COM2 COM1 SEG0–19 COM2 Not lit COM3 L1, L2 0–19 Fig. 4.6.5 Frame frequency Drive waveform for 1/3 duty (1/2 bias) LCD lighting status COM0 COM0 L1, L2 COM1 COM1 SEG0–19...
  • Page 48: Cadence Adjustment Of Oscillation Frequency

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) In the E0C6001 Series, the LCD drive duty can be set to Cadence adjust- 1/1 duty by software. This function enables easy adjust- ment of oscillation ment (cadence adjustment) of the oscillation frequency of frequency the OSC circuit.
  • Page 49: Mask Option (Segment Allocation

    Mask option (1) Segment allocation (segment allocation) As shown in Figure 4.l.1, the E0C6001 Series display data is decided by the display data written to the display memory (write-only) at address 090H–0AFH. The address and bits of the display memory can be made to correspond to the segment pins (SEG0–SEG19) in any...
  • Page 50 The pin pairs are the combination of SEG (2 * n) and SEG (2 * n + 1) (where n is an integer from 0 to 12). (4) Drive bias For the drive bias of the E0C6001 or the E0C60L01, either 1/3 bias or 1/2 bias can be selected by the mask option.
  • Page 51: Control Of Lcd Driver

    E0C6001 TECHNICAL HARDWARE Table 4.6.2 shows the control bits of the LCD driver and Control of LCD their addresses. Figure 4.6.10 shows the display memory driver map. Table 4.6.2 Control bits of LCD driver Register Address Comment Name CSDC Static...
  • Page 52: Clock Timer

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Clock Timer Configuration of The E0C6001 Series have a built-in clock timer driven by the source oscillator. The clock timer is configured as a clock timer seven-bit binary counter that serves as a frequency divider taking a 256 Hz source clock from the dividing circuit.
  • Page 53: Interrupt Function

    E0C6001 TECHNICAL HARDWARE The clock timer can interrupt on the falling edge of the 32 Interrupt function Hz, 8 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.7.2 is the timing chart of the clock timer.
  • Page 54: Control Of Clock Timer

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.7.1 shows the clock timer control bits and their Control of clock addresses. timer Table 4.7.1 Control bits of clock timer Register Address Comment Name High – Timer data (clock timer 2 Hz) High –...
  • Page 55 E0C6001 TECHNICAL HARDWARE EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0–D2) These registers are used to mask the clock timer interrupt. When 1 is written: Enabled When 0 is written: Masked Reading: Valid The interrupt mask register bits (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).
  • Page 56: Heavy Load Protection Function

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function) 4.8 Heavy Load Protection Function The E0C6001 Series have a heavy load protection function Operation of heavy for when the battery load becomes heavy and the supply load protection voltage drops, such as when an external buzzer sounds or function an external lamp lights.
  • Page 57: Control Of Heavy Load Protection Function

    E0C6001 TECHNICAL HARDWARE Table 4.8.1 shows the control bits and their addresses for Control of heavy the heavy load protection function. load protection function Table 4.8.1 Control bits for heavy load protection function Register Address Comment Name HLMOD HLMOD Heavy...
  • Page 58: Interrupt And Halt

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Interrupt and HALT The E0C6001 Series provide the following interrupt settings, each of which is maskable. External interrupt: Input interrupt (one) Internal interrupt: Timer interrupt (one) To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask registers must be set to 1 (enable).
  • Page 59 E0C6001 TECHNICAL HARDWARE Interrupt vector (MSB) Program counter of CPU (three low-order bits) (LSB) EIK00 (Interrupt request) EIK01 EIK02 EIK03 Interrupt factor flag EIT2 Interrupt mask register EIT8 IT32 EIT32 Fig. 4.9.1 Configuration of interrupt circuit I-52...
  • Page 60: Interrupt Factors

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.9.1 shows the factors that generate interrupt re- Interrupt factors quests. The interrupt factor flags are set to 1 depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1.
  • Page 61: Specific Masks And Factor Flags For Interrupt

    E0C6001 TECHNICAL HARDWARE The interrupt factor flags can be masked by the correspond- Specific masks and ing interrupt mask registers. The interrupt mask registers factor flags for inter- are read/write registers. They are enabled (interrupt en- rupt abled) when 1 is written to them, and masked (interrupt disabled) when 0 is written to them.
  • Page 62: Control Of Interrupt

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Tables 4.9.3 shows the interrupt control bits and their Control of interrupt addresses. Table 4.9.3 Interrupt control bits Register Address Comment Name Enable Mask EIK03 EIK02 EIK01 EIK00 EIK03 Interrupt mask register (K03) Enable Mask EIK02...
  • Page 63: Chapter 5 Basic External Wiring Diagram

    E0C6001 TECHNICAL HARDWARE CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM (1) Piezo Buzzer Single Terminal Driving PANEL Connection depending on power supply and LCD panel specification. Please refer to page I-7. OSC1 X'tal OSC2 1.5 V 3.0 V RESET TEST Piezo...
  • Page 64 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM (2) Piezo Buzzer Direct Driving PANEL Connection depending on power supply and LCD panel specification. Please refer to page I-7. OSC1 X'tal OSC2 1.5 V 3.0 V RESET TEST Piezo Buzzer X'tal Crystal oscillator 32.768 kHz CI(MAX) = 35 kΩ...
  • Page 65: Chapter 6 Electrical Characteristics

    E0C6001 TECHNICAL HARDWARE CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating =0V) Item Symbol Rated Value Unit Power voltage -5.0 to 0.5 Input voltage (1) Vss-0.3 to 0.5 Input voltage (2) Vss-0.3 to 0.5 IOSC ∑I Permissible total output current °C...
  • Page 66: Recommended Operating Conditions

    CHAPTER 6: ELECTRICAL CHARACTERISTICS Recommended Operating Conditions E0C6001 (Ta=-20 to 70°C) Item Symbol Condition Unit Power voltage -3.6 -3.0 -1.8 Oscillation frequency Crystal oscillation 32.768 OSC1 CR oscillation, R=470kΩ OSC2 µF Booster capacitor µF Capacitor between V and V µF...
  • Page 67: Dc Characteristics

    E0C6001 TECHNICAL HARDWARE 6.3 DC Characteristics E0C6001 Unless otherwise specified =0 V, V =-3.0 V, fosc=32.768 kHz, Ta=25°C, V and V are internal voltages, and C =0.1 µF Item Condition Unit Symbol High level input voltage (1) K00–K03, P00–P03 0.2•Vss...
  • Page 68 CHAPTER 6: ELECTRICAL CHARACTERISTICS E0C60L01 Unless otherwise specified =0 V, V =-1.5 V, fosc=32.768 kHz, Ta=25°C, V and V are internal voltages, and C =0.1 µF Item Condition Unit Symbol High level input voltage (1) K00–K03, P00–P03 0.2•Vss High level input voltage (2) RESET 0.15•Vss Low level input voltage (1)
  • Page 69: Analog Circuit Characteristics And Power Current Consumption

    µA Power current During HALT Without panel load µA consumption During execution E0C6001 (Heavy Load Protection Mode) Unless otherwise specified =0 V, V =-3.0 V, fosc=32.768 kHz (crystal oscillation), Ta=25°C, C =25 pF, and V are internal voltages, and C =0.1 µF...
  • Page 70 CHAPTER 6: ELECTRICAL CHARACTERISTICS E0C60L01 (Normal Operating Mode) Unless otherwise specified =0 V, V =-1.5 V, fosc=32.768 kHz (crystal oscillation), Ta=25°C, C =25 pF, and V are internal voltages, and C =0.1 µF Item Condition Unit Symbol Internal voltage Connect 1MΩ load resistor between V and V (without panel load) Connect 1MΩ...
  • Page 71 15.0 Without panel load µA consumption During execution 15.0 20.0 E0C6001 (CR, Heavy Load Protection Mode) Unless otherwise specified =0 V, V =-3.0 V, fosc=65 kHz, Ta=25°C, C =25 pF, V and V internal voltages, and C =0.1 µF, Recommended external resistance for CR oscillation=470 kΩ...
  • Page 72 CHAPTER 6: ELECTRICAL CHARACTERISTICS E0C60L01 (CR, Normal Operating Mode) Unless otherwise specified =0 V, V =-1.5 V, fosc=65 kHz, Ta=25°C, C =25 pF, V and V internal voltages, and C =0.1 µF, Recommended external resistance for CR oscillation=470 kΩ Item Condition Unit Symbol...
  • Page 73: Oscillation Characteristics

    E0C6001 TECHNICAL HARDWARE 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions. Use the following characteristics are as reference values. E0C6001 Unless otherwise specified =0 V, V =-3.0 V, Crystal : C-002R (CI=35 kΩ), C =25 pF, C =built-in, Ta=25°C...
  • Page 74 CHAPTER 6: ELECTRICAL CHARACTERISTICS E0C6001 (CR) Unless otherwise specified =0 V, V =-3.0 V, R =470 kΩ, Ta=25°C Item Symbol Condition Unit Oscillation frequency dispersion fosc 65kHz Oscillation start voltage Vsta -1.8 Oscillation start time Vss=-1.8 to -3.6V Oscillation stop voltage Vstp -1.8...
  • Page 75: Chapter 7 Package

    E0C6001 TECHNICAL HARDWARE CHAPTER 7 PACKAGE 7.1 Plastic Package Plastic QFP12-48pin ±0.4 ±0.1 INDEX +0.1 0.18 –0.05 ±0.05 0.125 0° 10° ±0.2 I-68...
  • Page 76: Ceramic Package For Test Samples

    CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples DIP-64pin 81.3 64 63 34 33 Pin No. 31 32 Index Mark 2.54 78.7 (Unit: mm) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name N.C.
  • Page 77: Chapter 8 Pad Layout

    E0C6001 TECHNICAL HARDWARE CHAPTER 8 PAD LAYOUT Diagram of Pad Layout (0, 0) Chip size: 2,640 µm (X) x 2,180 µm (Y) I-70...
  • Page 78: Pad Coordinates

    CHAPTER 8: PAD LAYOUT 8.2 Pad Coordinates Pad No Pad Name Pad No Pad Name SEG0 -1,151 -644 COM0 -1,126 -923 SEG19 COM1 -988 -923 SEG18 COM2 -858 -923 SEG17 COM3 -727 -923 SEG16 -597 -923 SEG15 -119 -466 -923 SEG14 -249 -336...
  • Page 79 E0C6001 Technical Software...
  • Page 80 CONTENTS CHAPTER 1 CONFIGURATION ............II-1 E0C6001 Block Diagram ..........II-1 ROM Map ............... II-2 Interrupt Vectors ............. II-3 Data Memory Map ............II-4 CHAPTER 2 INITIAL RESET ..............II-9 Internal Register Status on Initial Reset ......II-9 Initialize Program Example ..........
  • Page 81 Examples of interrupt and halt control program ..II-48 CHAPTER 4 SUMMARY OF PROGRAMMING POINTS....... II-50 APPENDIX Table of Instructions ............II-54 The E0C6001 I/O Memory Map ........II-59 Table of the ICE6200 Commands ......... II-60 Cross-assembler Pseudo-instruction List ...... II-62...
  • Page 82: Chapter 1 Configuration

    CHAPTER 1: CONFIGURATION CHAPTER 1 CONFIGURATION E0C6001 Block Diagram System Reset 1,024 × 12 Control Core CPU E0C6200B Interrupt × Generator COM0 K00~K03 I Port COM3 SEG0 Driver Test Port TEST SEG19 I/O Port P00~P03 Power Controller O Port R00, R01...
  • Page 83: Rom Map

    E0C6001 TECHNICAL SOFTWARE ROM Map The E0C6001 has a built-in mask ROM with a capacity of 1,024 steps × 12 bits for program storage. The configuration of the ROM is shown in Figure 1.2.1. Bank 0 Program start address 00H step...
  • Page 84: Interrupt Vectors

    CHAPTER 1: CONFIGURATION Interrupt Vectors When an interrupt request is received by the CPU, the CPU initiates the following interrupt processing after completing the instruction being executed. (1) The address of the next instruction to be executed (the value of the program counter) is saved on the stack (RAM).
  • Page 85: Data Memory Map

    E0C6001 TECHNICAL SOFTWARE Data Memory Map The E0C6001 built-in RAM has 80 words of data memory, 32 words of display memory for the LCD, and I/O memory for controlling the peripheral circuit. When writing pro- grams, note the following: (1) Since the stack area is in the data memory area, take care not to overwrite the stack with data.
  • Page 86 CHAPTER 1: CONFIGURATION Table 1.4.1(a) I/O memory map 1 Register Address Comment Name High – High – 0E0H Input port (K00–K03) High – High – – High Timer data (clock timer 2 Hz) – High Timer data (clock timer 4 Hz) 0E4H High –...
  • Page 87 E0C6001 TECHNICAL SOFTWARE Table 1.4.1(b) I/O memory map 2 Register Address Comment Name 0EDH Interrupt factor flag (K00–K03) IT32 Interrupt factor flag (clock timer 2 Hz) 0EFH Interrupt factor flag (clock timer 8 Hz) IT32 Interrupt factor flag (clock timer 32 Hz)
  • Page 88 CHAPTER 1: CONFIGURATION Table 1.4.1(c) I/O memory map 3 Register Address Comment Name TMRST TMRST Reset – Reset Clock timer reset 0F9H HLMOD HLMOD Heavy Normal Heavy load protection mode register load load 0FAH CSDC Static Dynamic LCD drive switch CSDC 0FBH 0FCH...
  • Page 89 E0C6001 TECHNICAL SOFTWARE Table 1.4.1(d) I/O memory map 4 Register Address Comment Name XBZR XFOUT1 XFOUT0 XBZR 2 kHz 4 kHz Buzzer frequency control 0FDH XFOUT1 High FOUT frequency control: XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT0 High XFOUT1(1), XFOUT0(0) ->...
  • Page 90: Chapter 2 Initial Reset

    CHAPTER 2: INITIAL RESET CHAPTER 2 INITIAL RESET Internal Register Status on Initial Reset Following an initial reset, the internal registers and internal data memory area are initialized to the values shown in Tables 2.1.1 and 2.1.2. Table 2.1.1 Internal Register Bit Length Initial Value Following Reset Initial values of internal...
  • Page 91 E0C6001 TECHNICAL SOFTWARE After an initial reset, the program counter page (PCP) is initialized to 1H, and the program counter step (PCS), to 00H. This is why the program is executed from step 00H of the first page. The initial values of some internal registers and internal data memory area locations are undefined after a reset.
  • Page 92: Initialize Program Example

    CHAPTER 2: INITIAL RESET Initialize Program Example The following is a program that clears the RAM and LCD, resets the flags, registers and timer, and sets the stack pointer immediately after resetting the system. Label Mnemonic/operand Comment 100H INIT Jump to "INIT" 110H INIT F,0011B...
  • Page 93 E0C6001 TECHNICAL SOFTWARE The above program is a basic initialization program for the E0C6001. The setting data are all initialized as shown in Table 2.1.1 by executing this program. When using this program, add setting items necessary for each specific application.
  • Page 94: Chapter 3 Peripheral Circuits

    CHAPTER 3: PERIPHERAL CIRCUITS (Input Port) CHAPTER 3 PERIPHERAL CIRCUITS Details on how to control the E0C6001 peripheral circuit is given in this chapter. Input Port Input port memory Table 3.1.1 I/O memory map Register Address Comment Name High –...
  • Page 95: Control Of The Input Port

    E0C6001 TECHNICAL SOFTWARE The E0C6001 has one 4-bit input port (K00–K03). Input port Control of data can be read as a 4-bit unit (K00–K03). the input port The state of the input ports can be obtained by reading the data (bits D3, D2, D1, D0) of address 0E0H. The input ports can be used to send an interrupt request to the CPU via the input interrupt condition flag.
  • Page 96 CHAPTER 3: PERIPHERAL CIRCUITS (Input Port) • Bit-unit checking of input ports Label Mnemonic/operand Comment Disable interrupt Y,0E0H Set address of port INPUT1: FAN MY,0010B NZ,INPUT1 Loop until K01 becomes "0" INPUT2: FAN MY,0010B Z,INPUT2 Loop until K01 becomes "1" This program loopes until a rising edge is input to input port K01.
  • Page 97: Output Port

    *4 Reset (0) immediately after being read *5 Always 0 when being read *6 Refer to main manual The E0C6001 Series have 2 bits for general output ports Control of (R00, R01). R00 and R01 although can be use for special the output port use output port as shown in later of this section.
  • Page 98: Examples Of Output Port Control Program

    CHAPTER 3: PERIPHERAL CIRCUITS (Output Port) • Loading B register data into R00, R01 Examples of output port control Label Mnemonic/operand Comment program Y,0F3H Set address of port R00, R01 ← B register MY,B As shown in Figure 3.2.1, the two instruction steps above load the data of the B register into the output ports.
  • Page 99 E0C6001 TECHNICAL SOFTWARE • Bit-unit operation of output ports Label Mnemonic/operand Comment Y,0F3H Set address of port MY,0010B Set R01 to 1 MY,1110B Set R00 to 0 The three instruction steps above cause the output port to be set, as shown in Figure 3.2.2.
  • Page 100: Special Use Output Port

    CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Port) Special Use Output Port Special use output port memory map Table 3.3.1 I/O memory map Register Address Comment Name BUZZER FOUT High R01 output port data 0F3H BUZZER Buzzer ON/OFF control register High R00 output port data FOUT...
  • Page 101: Control Of The Special Use Output Port

    E0C6001 TECHNICAL SOFTWARE In addition to the regular DC, special output can be selected Control of the spe- for output ports R00 and R01, as shown in Table 3.3.2. cial use output port Figure 3.3.1 shows the structure of output ports R00 and R01.
  • Page 102: Examples Of Special Use Output Port Control Program

    CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Port) • Buzzer driver output (BUZZER) Examples of special use output port When output port R01 is set for BUZZER and R00 is set for control program BUZZER, it performs 2,048 Hz or 4,096 Hz selected by register XBZR (0FDH D3).
  • Page 103 E0C6001 TECHNICAL SOFTWARE • Internal divided frequency output (FOUT) When output port R00 is set to FOUT output, fosc or clock frequency divided into fosc is generated. Clock frequency may be selected individually for F1–F4, from among 5 types by mask option; a clock frequency is then selected from 4 types (i.e., F1–F4) through XFOUT0 and XFOUT1 (0FDH D0...
  • Page 104: I/O Port

    CHAPTER 3: PERIPHERAL CIRCUITS (I/O Port) 3.4 I/O Port I/O port memory Table 3.4.1 I/O memory map Register Address Comment Name High – – High 0F6H I/O port (P00–P03) High – – High 0FCH Output Input I/O port P00–P03 Input/Output *1 Initial value following initial reset *2 Not set in the circuit *3 Undefined...
  • Page 105: Control Of The I/O Port

    E0C6001 TECHNICAL SOFTWARE The E0C6001 contains a 4-bit general I/O port (4 bits × 1). Control of This port can be used as an input port or an output port, the I/O port according to I/O port control register IOC. When IOC is "0", the port is set for input, when it is "1", the port is set for...
  • Page 106: Examples Of I/O Port Control Program

    CHAPTER 3: PERIPHERAL CIRCUITS (I/O Port) • Loading P00–P03 input data into A register Examples of I/O port control program Label Mnemonic/operand Comment Y,0FCH Set address of I/O control port MY,1110B Set port as input port Y,0F6H Set address of port A register ←...
  • Page 107 E0C6001 TECHNICAL SOFTWARE • Loading P00–P03 output data into A register Label Mnemonic/operand Comment Y,0FCH Set the address of input/output port control register MY,0001B Set as output port Y,0F6H Set the address of port A register ← P00–P03 A,MY As shown in Figure 3.4.2, the four instruction steps above load the data of the I/O ports into the A register.
  • Page 108 CHAPTER 3: PERIPHERAL CIRCUITS (I/O Port) • Loading contents of B register into P00–P03 Label Mnemonic/operand Comment Y,0FCH Set the address of input/output port control register MY,0001B Set port as output port Y,0F6H Set the address of port P00–P03 ← B register MY,B As shown in Figure 3.4.3, the four instruction steps above load the data of the B register into the I/O ports.
  • Page 109: Lcd Driver

    E0C6001 TECHNICAL SOFTWARE LCD Driver LCD driver memory Table 3.5.1 I/O memory map Register Address Comment Name Static Dynamic CSDC CSDC LCD drive switch 0FBH *1 Initial value following initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read...
  • Page 110: Control Of The Lcd Driver

    CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) The E0C6001 contains 128 bits of display memory in ad- Control of the LCD dresses 090H to 0AFH of the data memory. Each display driver memory can be assigned to any 80 bits of the 128 bits for the LCD driver (20 SEG ×...
  • Page 111 E0C6001 TECHNICAL SOFTWARE LCD lighting status COM0 COM1 COM2 0–3 COM3 Frame frequency SEG0–19 Not lit 0–19 Fig. 3.5.2 1/1 duty drive control (1/3 bias) Register Address 090H 091H Fig. 3.5.3 7-segment LCD assignment In the assignment shown in Figure 3.5.3, the 7-segment display pattern is controlled by writing data to display memory addresses 090H and 091H.
  • Page 112: Examples Of Lcd Driver Control Program

    CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) • Displaying 7-segment Examples of LCD driver control The LCD display routine using the assignment of Figure program 3.5.3 can be programmed as follows. Label Mnemonic/operand Comment 000H RETD 0 is displayed RETD 1 is displayed RETD 2 is displayed RETD...
  • Page 113 E0C6001 TECHNICAL SOFTWARE • Bit-unit operation of the display memory Data Address Fig. 3.5.5 Example of segment 090H : SEG-A assignment : SEG-B Label Mnemonic/operand Comment X,SEGBUF Set address display memory buffer Y,090H Set address display memory MX,3 Set buffer data...
  • Page 114: Timer

    CHAPTER 3: PERIPHERAL CIRCUITS (Timer) 3.6 Timer Timer memory map Table 3.6.1 I/O memory map Register Address Comment Name High – Timer data (clock timer 2 Hz) High – Timer data (clock timer 4 Hz) 0E4H High – Timer data (clock timer 8 Hz) High –...
  • Page 115: Control Of The Timer

    E0C6001 TECHNICAL SOFTWARE The E0C6001 contains a timer with a basic oscillation of Control of the timer 32.768 kHz (typical). This timer is a 4-bit binary counter, and the counter data can be read as necessary. The counter data of the 16 Hz clock can be read by reading TM3 to TM0 (address 0E4H, D3 to D0).
  • Page 116: Examples Of Timer Control Program

    CHAPTER 3: PERIPHERAL CIRCUITS (Timer) • Initializing the timer Examples of timer control program Label Mnemonic/operand Comment Y,0F9H Set address of the timer reset register MY,0100B Reset the timer The two instruction steps above are used to reset (clear TM0–TM3 to 0) and restart the timer. The TMRST register is cleared to "0"...
  • Page 117 E0C6001 TECHNICAL SOFTWARE • Checking timer edge Label Mnemonic/operand Comment X,TMSTAT Set address of the timer edge counter MX,0 Check whether the timer edge counter is "0" Z,RETURN Jump if "0" (Z-flag is "1") Y,0E4H Set address of the timer...
  • Page 118: Heavy Load Protection Function

    *4 Reset (0) immediately after being read *5 Always 0 when being read *6 Refer to main manual The E0C6001 has the heavy load protection function for Heavy load protec- when the battery load becomes heavy and the source voltage...
  • Page 119: Examples Of Heavy Load Protection Function Control Program

    E0C6001 TECHNICAL SOFTWARE • Operation through the HLMOD register Examples of heavy This is a sample program when lamp is driven with the load protection R00 terminal during performance of heavy load protec- function control tion. program Label Mnemonic/operand Comment...
  • Page 120: Interrupt And Halt

    CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) 3.8 Interrupt and Halt Interrupt memory Table 3.8.1 I/O memory map Register Address Comment Name Enable Mask EIK03 EIK02 EIK01 EIK00 EIK03 Interrupt mask register (K03) Enable Mask EIK02 Interrupt mask register (K02) 0E8H Enable Mask...
  • Page 121: Control Of Interrupts And Halt

    E0C6001 TECHNICAL SOFTWARE The E0C6001 supports two types of a total of 7 interrupts. Control of interrupts There are three timer interrupts (2 Hz, 8 Hz, 32 Hz) and four and halt input interrupts (K00–K03). The 7 interrupts are individually enabled or masked (dis- abled) by interrupt mask registers.
  • Page 122 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) • Interrupt factor flags This flag is set when any of the K00 to K03 input interrupts occurs. The interrupt factor flag (IK0) is set to "1" when the contents of the input (K00–K03) become "1" and the data of the corresponding interrupt mask register (EIK00–EIK03) is "1".
  • Page 123 E0C6001 TECHNICAL SOFTWARE This flag is set to "1" when a falling edge is detected in the IT32 timer TM1 (32 Hz) signal. The contents of the IT32 flag can be loaded by software to determine whether a 32 Hz timer interrupt has occured.
  • Page 124 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) • Interrupt mask registers The interrupt mask registers are registers that individually specify whether to enable or mask the timer interrupt (2 Hz, 8 Hz, 32 Hz) or input interrupt (K00–K03). The following are descriptions of the interrupt mask regis- ters.
  • Page 125 E0C6001 TECHNICAL SOFTWARE EIT32 This register enables or masks the 32 Hz timer interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIT32) is set to "1" and the inter- rupt condition flag (IT32) is "1". (See Figure 3.8.2.) EIT8 This register enables or masks the 8 Hz timer interrupt.
  • Page 126 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) • Interrupt vector address The E0C6001 interrupt vector address is made up of the low-order 2 bits of the program counter (12 bits), each of which is assigned a specific function as shown in Figure 3.8.4.
  • Page 127 E0C6001 TECHNICAL SOFTWARE If the EI instruction is executed without resetting the inter- rupt factor flag after generating the timer interrupt, and if the corresponding interrupt mask register is still "1", the same interrupt is generated once more. (See Figure 3.8.5.) If the EI state is set without resetting the interrupt factor flag after generating the input interrupt (K00–K03), the same...
  • Page 128 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Interrupt vector (MSB) Program counter of CPU (three low-order bits) (LSB) EIK00 (Interrupt request) EIK01 EIK02 EIK03 Interrupt factor flag EIT2 Interrupt mask register EIT8 IT32 EIT32 Fig. 3.8.5 Internal interrupt circuit II-47...
  • Page 129: Examples Of Interrupt And Halt Control Program

    E0C6001 TECHNICAL SOFTWARE • Restart from halt state by interrupt Examples of interrupt and halt control Main routine program Label Mnemonic/operand Comment X,0E8H Set address of K00 to K03 interrupt mask register MX,1111B Enable K00 to K03 input interrupt X,0EBH...
  • Page 130 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) TI32RQ: Y,TMFSK Address of timer factor flag buffer MY,0001B ; Check 8 Hz timer interrupt Z,IK0RQ Jump if not 32 Hz timer interrupt CALL TINT32 Call 32 Hz timer interrupt service routine IK0RQ: X,0EDH Address of K00 to K03 input interrupt flag MX,0001B ;...
  • Page 131: Chapter 4 Summary Of Programming Points

    E0C6001 TECHNICAL SOFTWARE CHAPTER 4 SUMMARY OF PROGRAMMING POINTS After the system reset, only the program counter (PC), • Core CPU new page pointer (NPP) and interrupt flag (I) are initial- ized by the hardware. The other internal circuits whose settings are undefined must be initialized with the pro- gram.
  • Page 132 CHAPTER 4: SUMMARY OF PROGRAMMING POINTS – When modifying the input port from high level to low level • Input Port with pull-down resistance, a delay will occur at the rise of the waveform due to time constant of the pull-down resistance and input gate capacities.
  • Page 133 E0C6001 TECHNICAL SOFTWARE – When the I/O port is set to the output mode and a low- • I/O Port impedance load is connected to the port pin, the data written to the register may differ from the data read.
  • Page 134 CHAPTER 4: SUMMARY OF PROGRAMMING POINTS – Re-start from the HALT state is performed by the inter- • Interrupt rupt. The return address after completion of the interrupt processing in this case will be the address following the HALT instruction. –...
  • Page 135: Appendix A Table Of Instructions

    E0C6001 TECHNICAL SOFTWARE APPENDIX Table of Instructions Operation Code Flag Mne- Classification Operand Clock Operation monic I D Z C ← ← Branch PSET p4, NPP p3~p0 ← ← ← instructions NBP, PCP NPP, PCS s7~s0 ← ← ← C, s...
  • Page 136 APPENDIX Operation Code Flag Mne- Classification Operand Clock Operation monic I D Z C ↑ ↑ ↓ ↓ Index XH, i XH-i3~i0 ↑ ↑ ↓ ↓ operation XL, i XL-i3~i0 ↑ ↑ ↓ ↓ instructions YH, i YH-i3~i0 ↑ ↑ ↓...
  • Page 137 E0C6001 TECHNICAL SOFTWARE Operation Code Flag Mne- Classification Operand Clock Operation monic I D Z C ← ← Stack M(SP), SP SP+1 ← ← operation M(SP), SP SP+1 ↑ ↑ ↑ ↑ ← ← ↓ ↓ ↓ ↓ instructions M(SP), SP SP+1 ←...
  • Page 138 APPENDIX Abbreviations used in the explanations have the following meanings. A ....A register Symbols associated with B ....B register registers and memory X ....X register (low order eight bits of index register Y ....Y register (low order eight bits of index register IY) XH ...
  • Page 139 E0C6001 TECHNICAL SOFTWARE NBP ..New bank pointer Symbols associated with program counter NPP ..New page pointer PCB ..Program counter bank PCP ..Program counter page PCS ..Program counter step PCSH .. Four high order bits of PCS PCSL ...
  • Page 140: The E0C6001 I/O Memory Map

    APPENDIX APPENDIX The E0C6001 I/O Memory Map DATA COMMENT DRESS NAME – HIGH INPORT DATA K03 – HIGH INPORT DATA K02 – HIGH INPORT DATA K01 – HIGH INPORT DATA K00 – HIGH CLOCK TIMER DATA 2 Hz – HIGH CLOCK TIMER DATA 4 Hz –...
  • Page 141: Table Of The Ice6200 Commands

    E0C6001 TECHNICAL SOFTWARE APPENDIX Table of the ICE6200 Commands Item No. Function Command Format Outline of Operation Assemble #A,a Assemble command mnemonic code and store at address "a" Disassemble #L,a1,a2 Contents of addresses a1 to a2 are disassembled and displayed...
  • Page 142 APPENDIX Item No. Function Command Format Outline of Operation History #H,p1,p2 Display history data for pointer 1 and pointer 2 Display upstream history data Display 21 line history data Display history pointer #HPS,a Set history pointer #HC,S/C/E Sets up the history information acquisition before (S), before/after (C) and after (E) #HA,a1,a2 Sets up the history information acquisition from program area...
  • Page 143: Cross-Assembler Pseudo-Instruction List

    E0C6001 TECHNICAL SOFTWARE APPENDIX Cross-assembler Pseudo-instruction List Item No. Pseudo-instruction Meaning Example of Use To allocate data to label (Equation) ABC+1 To define location counter 100H (Origin) To allocate data to label 0001H (Set) (data can be changed) 0002H To define ROM data...
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  • Page 146 ELECTRONIC DEVICES MARKETING DIVISION Electronic devices information on the Epson WWW server http://www.epson.co.jp First issue FEBRUARY 1997, Printed AUGUST 1998 in Japan...