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Digital Modules FAST - SPEED-Bus
321-1BH70 - DI 16xDC 24V > Process interrupt
6.3.2 Process interrupt
96
Byte 44 ... 47
Byte
Bit 7 ... Bit 0
44
2. edge evaluation (1 = edge detected, 0 = no edge detected). Here the last
presence of an edge since the last read access to the FA1 register is stored.
After a read access to this register (in the module) the register is not reset.
n
Bit 0: Status I+0.0
n
...
n
Bit 7: Status I+0.7
45
Edge evaluation
n
Bit 0: Status I+1.0
n
...
n
Bit 7: Status I+0.7
46...47
reserved
For guarantee of consistency of a µs ticker entry to the 1. edge evaluation (FA1) the 2.
edge evaluation (FA2) serves for. The consistency is ensured only if the appropriate bit of
the FA2 is "0". Since the last read access if more than one edge change took place, the
corresponding bit of edge lost (FV) is set. Here the µs ticker entry contains the time of the
last edge.
Example:
Byte
+1
FA1
4
0
FV
8
0
...
FA2
44
0
The consistent µs ticker entries can be determined by logical bit operations: FA1 AND
NOT FA2
Result
0
bit operation:
Depending to the system, the SFC 14 (DPRD_DAT) "Read consistent
data" cannot be used with this module.
Via the edge selection you may activate a process interrupt in your parameterization and
define on which edge of the input signal a process interrupt should be initialized. A
process interrupt causes a call of the OB 40. Within the OB 40 you may find the logical
basic address of the module that initialized the process interrupt by using the Local word
6. More detailed information about the initializing event is to find in the local double word
8.
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
VIPA System 300S
+0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
HB140 | SM-DIO | | en | Rev. 16-43
1
1
0
0
1
0
0
1
0
1
0
0
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