Mdio Ra 17 (Vendor Specific)-Channel Configuration And Status Register; Channel Configuration And Status Register (Mdio Ra 17) - Motorola MC92603 Reference Manual

Quad gigabit ethernet transceiver
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4.2.10 MDIO RA 17 (Vendor Specific)—Channel Configuration
and Status Register
MDIO RA 17 contains the MC92603 channel configuration and status register. These bits
are initially loaded on power up from the corresponding states of the external MC92603
configuration input pins. They may be modified through the MDIO interface. It is not
necessary to reset the device logic if these bits are modified. Figure 4-9 shows the content
of register 17.
15
R
i_xcvr_
m_xcvr_
disable
disable
W
Reset
XCVR_x_
0
DISABLE
7
R
W
Reset
0
Figure 4-9. Channel Configuration and Status Register (MDIO RA 17)
Table 4-7 lists the corresponding field descriptions for the channel configuration and status
register.
Table 4-7. Channel Configuration and Status Register Field Descriptions
Bits
Name
15
m_xcvr_disable
14
i_xcvr_x_disable
13
overrun
12
underrun
11
an_mode
10
recv_clk_cent
MOTOROLA
14
13
12
overrun
underrun an_mode
0
0
6
5
4
Receiver Error Counter
0
0
0
Initialized to zero. May be written through the MDIO interface. A software disable, when
set indicates that channel is to be disabled to reduce power. The channel is disabled if
either bit 15 or 14 are set. (R/W)
Contains the value of the XCVR_x_DISABLE input. (R)
Bit 13 is initialized to zero and then is set to one only if this channel 'overruns' due to clock
mismatch between the transmitter and receiver. Once set this bit is 'sticky.' That is, it
remains set until register 17 is read through the MDIO interface. This bit may not be
written through the MDIO interface. (R, LH, SC)
Bit 12 is initialized to zero and then is set to one only if this channel 'underrun' due to clock
mismatch between the transmitter and receiver. Once set this bit is 'sticky.' That is, it
remains set until register 17 is read through the MDIO interface. This bit may not be
written through the MDIO interface. (R, LH, SC)
Initialized to zero. This bit is set whenever this channel's transmitter is in the
auto-negotiation mode. This bit may not be written through the MDIO interface. (R)
Initialized to RECV_CLK_CENT input. May be written through the MDIO interface. If set,
indicates that data out of the receiver is centered relative to the RECV_x_RCLK output.
(R/W)
Chapter 4. Management Interface (MDIO)
11
10
broadcast_
recv_clk_cent
RECV_CLK_
0
BROADCAST
CENT
3
2
0
0
1
Description
MDIO Registers
9
8
xcvr_x_rsel
mode
XCVR_x_
RSEL
1
0
0
0
4-11

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