Receiver Interface, Ddr Timing; Receiver, Ddr Timing Diagram (Tbie = Low Or Compat = Low) - Motorola MC92603 Reference Manual

7.3.2.2

Receiver Interface, DDR Timing

The following sections provides the receiver, DDR timing specifications for the MC92603.
7.3.2.2.1 Receiver, DDR Clock Timing (All Modes Except Ethernet RTBI
Modes)
Figure 7-5 provides the receiver interface DDR timing diagram when TBIE is negated low
or COMPAT is negated low.
RECV RCLK
_x_
RECV 3–0
_x_
RECV ERR
_x_
RECV DV
_x_
RECV COMMA
_x_
Figure 7-5. Receiver, DDR Timing Diagram (TBIE = Low or COMPAT = Low)
Table 7-9 provides the receiver, DDR timing specifications when TBIE is negated low or
COMPAT is negated low.
Table 7-9. Receiver, DDR Timing Specification (TBIE = Low or COMPAT = Low)
Symbol Characteristic
T Output valid time before rising/falling edge of
1
RECV_x_RCLK
T Output valid time after rising/falling edge of
2
RECV_x_RCLK
T RECV_x_RCLK cycle time
3
T RECV_x_RCLK half cycle time
4
1
10 pF output load.
2
Full speed, HSE = low.
3
Half speed, HSE = high.
MOTOROLA Chapter 7. Electrical Specifications and Characteristics
T T
1 2
Aligned Clock
1
Min
–0.500
–1.000
3.000
7.000
7.800
15.800
3.800
7.800
AC Electrical Characteristics
T
3
T
4
T
T
2
1
Centered Clock
Max Min Max
0.500 1.440 —
1.000 3.440 —
— 1.420 —
— 3.500 —
8.200 7.800 8.200
16.200 15.800 16.200
4.200 3.800 4.200
8.200 7.800 8.200
Unit Note
2
ns
3
ns
2
ns
3
ns
2
ns
3
ns
2
ns
3
ns
7-9