Receiver Interface Timing - Motorola MC92603 Reference Manual

AC Electrical Characteristics
7.3.2

Receiver Interface Timing

The data output timing at the receiver interface may be single data rate (non-DDR) or
double data rate (DDR) as described in Section 3.4, "Receiver Interface Configuration."
Additionally, the valid data is sourced simultaneously with, or centered on, the
RECV_x_CLK output, depending on the state of the control signal, RECV_CLK_CENT.
When the control signal RECV_CLK_CENT = high, the data is centered about the receiver
clock edge. When RECV_CLK_CENT = low, the receiver clock edge is aligned
(co-incident) with the data. See Section 3.6, "Receiver Interface Timing Modes," for more
on receiver interface timing.
Table 7-6 shows the receiver clock cycle time and the target or typical offset of the clock
edge with respect to the data depending on the device application configuration. Note that
the complement of the receiver clock, RECV_x_RCLK_B, is only valid and available in
TBI and RTBI Ethernet compliant applications modes.
Table 7-6 also lists references to timing figures in the following receiver interface timing
sections.
Table 7-6. Target Receiver Clock Offset Relative to Data
Application
DDR
Mode
GMII or 8-/10-bit Low
backplane
Low
Ethernet TBI Low
Low
RGMII or 4-/5-bit High
backplane
High
Ethernet RTBI High
High
1
Assumes 125-MHz reference clock if HSE is disabled and 62.5-MHz reference clock if HSE is enabled.
7-6
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
Receiver
TBIE and
Clock Cycle
COMPAT = HSE
Time
High
False Low
False High
True Low
True High
False Low
False High
True Low
True High
RECV_x_ RECV_x_
1
RCLK RCLK_B
(ns)
8 Valid
16 Valid
16 Valid Valid
32 Valid Valid
8 Valid
16 Valid
8 Valid Valid
16 Valid Valid
Clock Offset
Reference
to Data
Figure No.
(ns)
Low 4
Low 8
4
8
Low 2
Low 4
2
4
MOTOROLA
7-3
7-3
7-4
7-4
7-5
7-5
7-6
7-6