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MDIO Registers
The 2 least significant bits of the 5-bit address, MD_ADR1 and MD_ADR0, are used to
uniquely identify each MC92603 channel (00 indicates channel A, 01 = B, 10 = C, and
11 = indicates channel D).
The 2.5-MHz data interface clock, MD_CLK, is sourced at the MDIO master (MAC) and
is used by each slave MDIO device. The MC92603 is designed as MDIO slave devices.
The MDIO data signal, MD_DATA, is a bidirectional serial signal used to read and write
management data from/to the MDIO registers.
4.2
MDIO Registers
The specification calls for up to 64 registers to be supported by MDIO. Some registers must
be included to meet the minimum MDIO specification; they are identified as the basic
register set. Other registers are optional and are considered part of the extended register set.
The MC92603 has four sets of MDIO registers (one per transceiver channel). Registers for
address 0–6 and 15–18, as defined in the standard specification, are fully supported.
Registers 7–14 and 19–31 are not supported in the MC92603. The MDIO registers are
identified in Table 4-1.
MDIO Register
Address (RA)
0
Control
1
Status
2, 3
PHY identifier
4
Auto-negotiation advertisement
5
Auto-negotiation link partner base page ability
6
Auto-negotiation expansion
7
Auto-negotiation next page transmit
8
Auto-negotiation link partner received next page
9
Master-slave control register
10
Master-slave status register
11–14
Reserved
15
Extended status
16
Vendor specific—permanent configuration control
17
Vendor specific—channel configuration and status
18
Vendor specific—BERT error counter
19–31
Vendor specific—not implemented
4-2
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
Table 4-1. MDIO Management Register Set
Register Name
Basic/Extended
Supported by
Register Set
MC92603
B
Yes
E
No
B
Yes
E
No
MOTOROLA
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