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Functional Description
The input amplifier facilitates a loopback path for production and in-system testing. When
the MC92603 is in loopback mode (loopback enable, LBE, is high), the input amplifier
selects the loopback differential input signals and ignores the state on the RLINK_x_P and
RLINK_x_N signals. This allows in-system loopback BIST independent of the current
input state. See Chapter 6, "Test Features," for complete information on test modes.
3.3.2
Transition Tracking Loop and Data Recovery
The received differential data from the input amplifier is sent to the transition tracking loop
for data recovery. The MC92603 uses an oversampled transition tracking loop method for
data recovery.
The differentially received data is sampled and processed digitally to provide for low-bit
error rate (better than 10
The transition tracking loop is tolerant of frequency offset between the transmitter and
receiver. The MC92603 reliably operates with +250 ppm of frequency offset. The transition
tracking loop method is different than the typical PLL clock recovery method. Its receiver
compensates for overrun and underrun due to frequency offset. The receiver does this by
modulating the duty-cycle and period of the received byte clock so that it matches the
frequency of the received data (see Section 3.6.1, "Recovered Clock Timing Mode
(RCCE = High)," for more information).
Recovered data is accumulated into 10-bit characters. If a byte alignment mode is enabled
by asserting BSYNC high, the characters are aligned to their original 10-bit boundaries.
3.3.3
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the transition tracking loop and
decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of
error checking. First, it checks that all characters are legal members of the 8B/10B coding
space. The decoder also checks for running disparity errors. A disparity error is generated
if the running disparity exceeds the limits set in the 8B/10B coding standard.
An illegal character or disparity error asserts the RECV_x_ERR signal high, coincident
with the received data for a 1-byte output period. The 'code error' or 'disparity error' is
being reported as described in Table 3-10 and Table 3-15. It is difficult to determine the
exact byte that causes a disparity error, so the error should not be associated with a
particular received byte. Rather, it is a general indicator of the improper operation of the
link. Use of the disparity error is provided so the system can monitor link reliability.
The 8B/10B decoder is bypassed when operating in 10-bit interface mode (TBIE asserted
high).
3-6
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
–12
).
MOTOROLA
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