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MDIO Registers
Table 4-7. Channel Configuration and Status Register Field Descriptions
Bits
Name
9
broadcast
8
xcvr_x_rsel
7–0
recv_error_ctr
1
LH = Latched high, R = read only, R/W = read and write, and SC = self-cleaning.
4.2.11 MDIO RA 18 (Vendor Specific)—BERT Error Counter
Register
The MDIO RA 18, shown in Figure 4-10, contains the MC92603 BERT error counter
register. These bits are initially cleared to all zeros. They may be read through the MDIO
interface. They are updated from the appropriate channel's BERT error counter when
running any of the BERT tests.
15
14
13
R
W
Reset
0
0
0
Figure 4-10. BERT Error Counter Register (MDIO RA 18)
4-12
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
Initialized to BROADCAST input if in redundant mode (ENAB_RED input is high). May be
written through the MDIO interface if in redundant mode. If set indicates that data will be
transmitted over both of the transmit links. Only applicable to Channel A and B. (R/W)
Initialized to XCVR_x_RSEL input if in redundant mode (ENAB_RED input is high). May
be written through the MDIO interface. If set indicates that data will be
transmitted/received over the secondary (redundant) links. Only applicable to Channel A
and B. (R/W)
Initialized to zero. This 8-bit counter is incremented whenever this channel's receiver
detects a code error or disparity error. This counter is cleared when read through the
MDIO interface. This counter cannot be loaded (other than cleared) through the MDIO
interface. If counter reaches maximum value (0xFF) it will not roll over to zero; instead it
will stay at this value until read. This register is to give a quick (although not precisely
accurate) reading on bit error rate. Implementation limitations may cause some errors not
to be counted. (R, SC)
12
11
10
9
Reserved
0
0
0
0
1
Description
8
7
6
5
BERT Error Counter Value
0
0
0
0
4
3
2
1
0
0
0
0
MOTOROLA
0
0
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