Receiver Interface, Non-Ddr Clock Timing (Ethernet Tbi Mode); Receiver, Non-Ddr Timing Diagram (Tbie = High And Compat = High) - Motorola MC92603 Reference Manual

AC Electrical Characteristics
7.3.2.1.2

Receiver Interface, Non-DDR Clock Timing (Ethernet TBI Mode)

Figure 7-4 provides the receiver interface, non-DDR timing diagram when TBIE is asserted
high and COMPAT is asserted high.
RECV_x_RCLK
RECV_x_RCLK_B
RECV_x_7–0
RECV_x_ERR
RECV_x_DV
RECV_x_COMMA
Figure 7-4. Receiver, Non-DDR Timing Diagram
Table 7-8 provides the receiver, non-DDR timing specifications when TBIE is asserted
high and COMPAT is asserted high.
Table 7-8. Receiver, Non-DDR Timing Specifications
Symbol Characteristic
T1 Output valid time before rising edge of
RECV_x_RCLK or RECV_x_RCLK_B
T2 Output valid time after rising edge of
RECV_x_RCLK or RECV_x_RCLK_B
T3 RECV_x_RCLK or RECV_x_RCLK_B cycle
time
T4 Rising edge of RECV_x_RCLK to rising
edge of RECV_x_RCLK_B
1
10 pF output load.
2
Full-speed, HSE = low.
3
Half-speed, HSE = high.
7-8
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
T
1
(TBIE = High and COMPAT = High)
(TBIE = High and COMPAT = High)
Aligned Clock
1
Min
–0.500
–1.000
7.000
15.000
15.80
31.80
7.80
15.80
T
3
T
4
T T T
2 1 2
Centered Clock
Max Min
0.500 3.500
1.000 7.500
— 3.500
— 7.500
16.20 15.800
32.20 31.800
8.20 7.800
16.20 15.800
Unit Note
Max
2
— ns
3
— ns
2
— ns
3
— ns
2
— ns
3
— ns
2
8.200 ns
3
16.200 ns
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