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Chapter 4
Management Interface (MDIO)
This chapter consists of the following sections:
• Section 4.1, "MDIO Interface"
• Section 4.2, "MDIO Registers"
The management data input/output (MDIO) interface as defined in Clause 22 of IEEE Std.
802.3-2002 [4] is supported by the MC92603 Quad Gigabit Ethernet transceiver. Details
for protocol and electrical characteristics are available in the standard.
This chapter provides details on the MDIO interface signals and their associated registers.
The MDIO is accessible in all of the backplane or Ethernet compatibility operational
modes.
4.1
MDIO Interface
The MC92603 chip MDIO interface consists of one enable input, five address inputs, one
clock input, and one bidirectional data signal.
Some users may wish to use the MDIO interface, and others may not. If the MDIO interface
is to be used then the MDIO enable input, MDIO_EN, must be asserted high. The MDIO
interface is available whether COMPAT is enabled or not.
On power up, the MC92603 will always assume the default configuration defined by the
pins of the device. The configuration can then be changed through the MDIO interface
regardless of the application operating mode. If MDIO is not used (MDIO_EN is low), the
MC92603 will operate in the default configuration.
The MDIO interface is a multidrop serial interface and each part must have a unique PHY
address. Each channel is addressed separately in the MC92603. The base address to each
transceiver must be mod 4. This address is read from three input pins that must be externally
pulled up or pulled down to furnish a unique address for each part that is connected to a
MDIO bus. These three address inputs are identified as: MD_ADR4, MD_ADR3, and
MD_ADR2.
MOTOROLA
Chapter 4. Management Interface (MDIO)
4-1
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