Keysight N5264A Service Manual page 70

Theory of Operation
Synthesized LO Group Operation (Option 108)
— to provide ALC signals to the A21 HMA26.5.
Rear Panel Interconnects
The A19 test set motherboard includes the following rear panel interconnects.
TEST SET I/O
HANDLER I/O
PWR I/O
Table 5-1 TEST SET I/O Connector Pin Assignments
DB-25 Female Connector
Pin Numbers Name
1 SEL0
2 Sweep Holdoff In
3–6 AD12–AD8
7 GND
8 LAS
9–11 AD4–AD2
12 GND
13 Interrupt In
14 +22 V
15–16 SEL1–2
17 AD11
5-8
A DB-25 female connector that is used to control external test sets. The external test set bus
consists of 13 multiplexed address and data lines, three control lines, and an open-collector
interrupt line. Pin assignments are listed in
Up to 16 test sets may be "daisy-chained" on the bus at one time.
The Test Set I/O is not compatible with 8753 network analyzer test sets.
A rectangular 36-pin, female connector providing four independent parallel input/output
ports, nine control signal lines, one ground, and a power supply line. This connector has Type
2 output pin assignments as listed in
All signals are TTL-compatible. Data input/output ports consist of two 8-bit output ports (Port
A and Port B) and two 4-bit bidirectional ports (Port C and Port D).
Connector settings can be changed using SCPI and COM commands. The settings are not
accessible from the front panel.
A DB-9 female connector. Pin assignments are listed in
Function
TTL out, test set select bit 0, tied to 0 V
TTL in, low level holds off sweep
TTL I/O, address and latched data
0 V, ground reference
TTL out, active low address strobe (1 s min)
TTL I/O, address and latched data
0 V, ground reference
TTL in, low level (10 s min) aborts sweep
+22 Vdc, 100 mA max.
TTL out, test set select bits 1-2, tied to 0 V
TTL I/O, address and latched data
Table 5-1 on page 5-8
Table 5-2 on page 5-9
Table 5-3 on page 5-10
Keysight N5264A Service Guide
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