Command Completion Coalescing Control Register (Ccc_Ctl); Command Completion Coalescing Control Register (Ccc_Ctl) Field Descriptions - Texas Instruments AM1808 Technical Reference Manual

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28.4.6 Command Completion Coalescing Control Register (CCC_CTL)

The command completion coalescing control register (CCC_CTL) is used to configure the command
completion coalescing (CCC) feature for the SATASS core. It is reset on Global reset. The CCC_CTL is
shown in Figure 28-6
Figure 28-6. Command Completion Coalescing Control Register (CCC_CTL)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28-10. Command Completion Coalescing Control Register (CCC_CTL) Field Descriptions
Bit Field Value
31-16 TV 0-FFFFh
15-8 CC 0-FFh
7-3 INT 0-1Fh
2-1 Reserved
0 EN
SPRUH82C – April 2013 – Revised September 2016
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and described in Table
CC
R/W-1
Description
Time-out value. This bit field specifies the CCC time-out value in 1 ms intervals. Software loads
this value prior to enabling CCC. This bit field is:
• Read/Write (R/W) when EN = 0
• Read only (R) when EN = 1
A time-out value of 0 is reserved and should not be used.
Command Completions. This bit field specifies the number of command completions that are
necessary to cause a CCC interrupt. Software loads this value prior to enabling CCC. This bit field
is:
• Read/Write (R/W) when EN = 0
• Read only (R) when EN = 1
A value of 0 disables CCC interrupts being generated based on the number of commands
completed, that is, CCC interrupts are only generated based on the timer in this case.
Interrupt. This bit field specifies the interrupt used by the CCC feature, using the number of ports
configured for the core. For a single Port instantiation, INT should be programmed to 1.
When a CCC interrupt occurs, the IS.IPS[INT] bit is set to 1.
0 Reserved.
CCC feature enable. When EN = 1, software can not change the bit fields: TV and CC.
0 CCC feature is disabled and no CCC interrupts are generated.
1 CCC feature is enabled and CCC interrupts may be generated based on the time-out or command
completion conditions.
Copyright © 2013–2016, Texas Instruments Incorporated
28-10.
TV
R/W-1
8 7
INT
R-1
Registers
3 2 1
Reserved
R-0 R/W-0
Serial ATA (SATA) Controller
16
0
EN
1379