84Sig: Signal Input Board - Stanford Research Systems SR844 User Manual

6-12 Circuit Descriptions
MRNGS: Range Select
The SR844 operates in 13 octave ranges, from 25 kHz to 200 MHz. The ranges and the
associated bit values are defined in a table in the description of 84DVC below. In
internal reference mode, the host '186 processor knows what the instrument frequency
and range should be and writes the range to the up/down counter U849 directly. In
addition it writes the loop filter bits ILF0 and ILF1 (U848.10, U848.11). In external
mode the range is determined on the fly by the hardware as follows. VTUN2 is an input
from the 84XRF board that is equal to half the VCO tuning voltage. It is typically about
1.0V at the bottom of an octave (VCO at 200 MHz) and about 9.0V at the top of the
octave (VCO at 400 MHz). VTUN2 is compared against set points P840 and P842 by
comparators U840A and U840B. If VTUN2 is too low, then the circuit should try to
establish phase-lock on the next lower octave. In this case the LOWER input to U848
goes high, causing a down clock to be sent to counter U849, which decreases the range
by 1. Similarly if VTUN2 is too high, -RAISE goes low, and an up clock is sent to
U849, which increases the range by 1. R849/C849 delays the clock by 10ns to ensure
that the Down/Up control U849.5 is established before the clock edge arrives at
U849.14. In addition U852A generates an 80µs long pulse that disables further range
transitions for the 80µs duration. The trigger input to U852.2 is the clock pulse, buffered
by U851B and delayed 90ns by R851/C851. Were it not for the 90ns delay, the disable
pulse from U852 would shut off the clock pulse too soon; this delay ensures that the
clock to U849 is not a runt pulse.
U848 also writes the loop filter bits to 84XRF; these bits are determined by internal logic
from the range bits when the unit is in external mode, while the ILF0-1 bits written by
the host are used directly in internal mode. U848 also accepts RISING and -FALLING
as inputs from the phase comparator on 84XRF; if either is active the instrument is not
phase-locked and the unlock output UNLL is set high. Further, the range switching clock
is disabled if it would cause the range to go outside the endpoints (2,14). If a range
switch is necessary and the range is already at one of the endpoints, the out-of-range
output OORL is set. UNLL and OORL are latched within U848, they are cleared by
-LCHCLR after the host '186 processor has read the status register.
Comparator U840D compares VTUN2 against a mid-range setpoint to establish whether
the VCO frequency (and by inference the reference frequency) are in the upper or lower
half of an octave. This determines bit RANGR4 (low in lower half of octave, high in
upper half). In normal operation CALSEL and CALRNG4 are both low, and RANGR4 is
the inverse of the comparator output. In internal mode and certain other special
situations, the host '186 processor can override the hardware setting of this bit by writing
CALSEL high, in which case RANGR4 is equal to the value written for CALRNG4. These
bits, CALSEL and CALRNG4 are written to register U850 along with the range and loop
filter bits.

84SIG: Signal Input Board

The 84SIG board is located on the left-hand side front of the instrument. This board
contains the RF input signal circuitry, including attenuation, filtering and gain. The
input to the board is the raw signal provided by the user on the front panel signal input.
SR844 RF Lock-In Amplifier