Status Register Definitions - Stanford Research Systems SR844 User Manual

Status Register Definitions

The SR844 reports on its status by means of four status registers: the Serial Poll Status,
the Standard Event Status, the LIA Status and the Error Status.
The status bits are set to 1 when an event has occurred or a state is present, as described
in the tables below.
Serial Poll Status Register: *STB?, *SRE
bit name
0 SCN
1
2 ERR
3 LIA
4 MAV
5 ESB
6 SRQ
7 unused
Standard Event Status Register: *ESR?, *ESE
bit name
0 RXQ
1
2 TXQ
3
4 EXE
5 CMD
6 URQ
7 PON
Bits in this register remain set until cleared by reading them or by the *CLS command.
set when
No data storage is in progress. Paused storage is still considered to be in
progress.
IFC No command execution is in progress (Interface Ready).
An enabled bit in the Error status register has been set.
An enabled bit in the LIA status register has been set.
The interface output buffer is not empty.
An enabled bit in the Standard Event status register has been set.
A service request has occurred.
set when
Input queue overflows. This occurs when too many characters are
received at once and causes the queues to be cleared.
–– unused
Output queue overflows. This occurs when too many characters are
waiting to be transmitted and causes the queues to be cleared.
–– unused
Command execution error occurs.
Illegal command is received.
Any key-press or knob rotation.
Power-on.
Status Registers 4-31
SR844 RF Lock-In Amplifier