Stanford Research Systems SR844 User Manual page 182

6-16 Circuit Descriptions
amplifier stages. As with subsequent amplifier stages, a small capacitor in the feedback
loop provides weak roll-off for high-frequency signals.
U401 is a programmable amplifier stage, the gain of ×1, ×3, ×10, ×30 corresponds to
control bit values [IF1,IF0] = [0,0], [0,1], [1,0], [1,1] respectively. U403A is a
programmable amplifier stage, its gain ×1, ×10 corresponds to bit IF2 = 0,1
respectively. U403B is another ×1, ×10 stage identical to U403A; it is controlled by bit
IF3. The inputs to U403A and U403B are both AC-coupled to eliminate unwanted
amplification of DC offsets from preceding stages.
The IF bits are set by the instrument depending on the front panel settings. All Op amps
in this section and in the anti-aliasing filter have independent decoupled power supplies.
IFN1: Anti-Aliasing Filter (AAF)
Op amps U406–U408 constitute a 7th order Cauer low-pass filter with cutoff at 18 kHz.
This serves as an anti-aliasing filter. C422 is the filter termination. The filter output is
buffered by U410.
Switch U409A selects between (a) the AAF output and (b) the unfiltered output direct
from U403B. The latter is used when the user has selected NoFilter on the front panel.
The AAF is always connected to U403B, but the unfiltered line is disconnected by
switch U405A when not in use, in order to eliminate cross-talk.
U410A is a summing amplifier that sums the filtered/unfiltered signal with noise. The
option to turn the noise off with U409B is not available to the user. The addition of out-
of-band noise serves to improve the linearity and resolution of the measurement, without
adding noise within the measurement bandwidth. The output of U410A DET.X is ready
for digitizing and goes directly to the A-to-D converter.
IFN2: A-to-D Converter
U478 is a 2-channel A-to-D converter. Besides the conditioned signals DET.X and
DET.Y above, this I.C. requires control signals from the DSP board 84DSP. CONVERT is
a short pulse that triggers the data sampling and conversion process, ADC.CLK is a train
of 18 clocks that reads the data out of U478. The output data is a serial bit stream, MSB
first, for each of the X and Y channels. These bit streams, SER.X and SER.Y go to the
DSP board 84DSP for further (digital) processing.
IFN2: Overload Detector
U480 is a quad comparator used to check that the A-to-D signal inputs DET.X and DET.Y
are within ±2.5 V. The comparator outputs OVLD.X and OVLD.Y are TTL levels that go
low when the A-to-D is overloaded. The 2.5 V thresholds are generated from the A-to-D
RefOut of 2.75 V by op amps U479A,B.
SR844 RF Lock-In Amplifier