Stanford Research Systems SR844 User Manual page 189

Circuit Descriptions 6-23
indirectly the reference frequency. The DSP clock is fixed frequency 20 MHz, it comes
from the Synthesizer section of the motherboard and is buffered by U910. The
operations performed within the DSP are described in Chapter 2, Inside the DSP.
FPGA
U904 is the FPGA (Field Programmable Gate Array). This chip performs the following
functions (a) conversion of parallel data on the DSP data bus to and from serial data on
the A-to-D and D-to-A data lines (b) generation of all timing clocks and pulses required
for operation of the A-to-D's, D-to-A's, DSP data sampling, and the noise circuit on
84IFN. This chip is programmed over the instrument data bus D0–D7 each time the
instrument is powered up; the data bus is not used by the FPGA otherwise. U908 and
U910 buffer the outputs from the FPGA, and N908–N911 provide isolation.
The FPGA has four clock inputs :
[1] 6M+ is a synchronous (to the reference frequency and data sampling) clock that is
recovered from low-level inputs 6M12D± by comparator U905. These low-level (±200
mV) inputs come from the divider chain 84DVC. R905, Z905 provide termination to the
input lines. Because the input is always at high frequency, no hysteresis is required.
[2] 49K– is a synchronous clock which defines the instrument sampling rate; it is
recovered from low-level inputs 49K98D± (also from 84DVC) by comparator U938.
R938 provides hysteresis; no line termination is required.
[3] CCLK (U904.73) comes from the host '186 processor via the platform interface and is
only used for programming the FPGA.
[4] ICLKDSP is a buffered 20MHz clock identical to the DSP clock; it is presently
unused.
Auxiliary Input
The Auxiliary inputs AUXI0–AUXI3 are differential lines (two for each input) coming
from the rear panel BNCs, via connector J2 on the motherboard. U907A,B are two
differential amplifiers with ×0.25 gain that convert the differential ±10V inputs into
single-ended signals within the A-to-D converters' input range. U909 is a two-channel
A-to-D converter, its control signals are generated by the FPGA, and its serial bitstream
outputs (MSB first) go to the FPGA where they are converted to parallel data and read
by the DSP.
Auxiliary Output
U914 is a dual D-to-A converter, its control signals and serial input data are written
directly by the host '186 via the platform interface. R914 and Z913 filter the channel 2
output with a time constant of 47µs. The filtered output is amplified by U915A so as to
provide outputs spanning ±10V. The channel 1 circuitry is identical. The outputs go to
the rear panel BNCs via connector J2 on the motherboard.
SR844 RF Lock-In Amplifier