Stanford Research Systems SR844 User Manual page 135

Using *STB?
A bit in the Serial Poll Status register is not cleared by reading the register using *STB?
The bit stays set as long as the status condition exists. This is true even for SRQ. SRQ
will be set whenever the same bit in the Serial Poll Status register and Serial Poll Enable
register is set. This is independent of whether a serial poll has occurred to clear the
service request.
Using Status Enable Registers
The ERR, LIA and ESB bits are set whenever any bit in both their respective status
register and enable register is set. Use the *ESE, ERRE and LIAE commands to set
status enable register bits. This allows status bits in the Error, LIA and Standard Event
Status registers to set bits in the Serial Poll register where they can be serial polled or
cause a service request.
The ERR, LIA and ESB bits are not cleared until ALL enabled status bits in the Error, LIA
and Standard Event status registers are cleared. The status registers can be cleared by
reading them, or by using the *CLS command.
Service Requests (SRQ)
A GPIB Service Request (SRQ) will be generated whenever an enabled bit in the Serial
Poll Status register becomes set. Use *SRE to enable bits in the Serial Poll Status by
setting the corresponding bits in the Serial Poll Enable register. A service request is only
generated when an enabled Serial Poll Status bit becomes set (changes from 0 to 1). An
enabled status bit which becomes set and remains set will generate a single SRQ. If
another service request from the same status bit is desired, the requesting status bit must
first be cleared. In the case of ERR, LIA and ESB bits, this means clearing the enabled
bits in the ERR, LIA and ESB status registers (by reading them). Multiple enabled bits in
these status registers will generate a single SRQ. Another SRQ (from ERR, LIA or ESB)
can only be generated after clearing the ERR, LIA or ESB bits in the Serial Poll Status
register. To clear these bits, all enabled bits in the ERR, LIA or ESB status bytes must be
cleared.
The host computer should respond to the SRQ by performing a serial poll to each device
to determine which is requesting service (as indicated by SRQ set). Bit 6 (SRQ) will be
reset by the serial poll.
For example, to generate a request when a RSV overload occurs, bit 5 in the LIA Status
Enable register needs to be set (LIAE32 or LIAE5,1 command) and bit 3 in the Serial
Poll Enable register must be set (*SRE8) command. When a reserve overload occurs, bit
5 in the LIA Status is set. Since bit 5 in the LIA Status Enable register is also set, bit 3
(LIA) in the Serial Poll Status also gets set. Since bit 3 in the Serial Poll Enable register is
also set, an SRQ is generated. Bit 6 (SRQ) in the Serial Poll Status is set. Further RSV
overloads will not generate another SRQ until the RSV overload status bit is cleared. The
RSV status bit is cleared by reading the LIA Status register (LIAS? query). Presumably
the host is alerted to the overload via the SRQ, performs a serial poll to clear the SRQ,
does something to try to remedy the situation (change gain, experimental parameters, etc.)
and then clears the RSV status bit by reading the LIA Status register. A subsequent RSV
overload will then generate another SRQ.
Status Registers 4-33
SR844 RF Lock-In Amplifier