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MibSPI Operation Modes
Figure 1.
MibSPI Module Block Diagram
DMAreq
Int0/Int1
MIBspi
16
2
DMAreq
Buffer
Shift register
SIMO SOMI
4
Expansion bus
Multi-buffer RAM
access control unit
Tx
Ctrl
buffer
field
Sequencer
Ctrl & stat
info
Parity
CLK
ENA
SCS0
controller
External
event
Ctrl
13
regs
Event
mgmt
Stat
Rx
Tick
field
buffer
count
Buffer
array
mgmt
Ctrl regs
SCSx
DMA
MibSPI
interface
including
multi-buffer
RAM and
sequencer
MibSPI
kernel
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