Suspend Mode Support; Watchdog Timer Registers; Watchdog Timer Control Register 0; Watchdog Timer Control Register 1 - Infineon Technologies TC1784 User Manual

(WDT_SR.TIM) from 7FFF
the instruction following the instruction that was last executed before entering the Idle or
Sleep Mode.
Note: Before switching into a non-running power-management mode, software should
perform a Watchdog service sequence. At the Modify Access, the Watchdog
reload value, WDT_CON0.REL, should be programmed such that the wake-up
occurs after a period which best meets application requirements. The maximum
period between two CPU wake-ups is one-half of the maximum WDT period.
3.8.4.4

Suspend Mode Support

In an enabled and active debug session the Watchdog functionality can lead to
unintended resets. Therefore to avoid these resets the OCDS can control if the WDT is
enabled or disabled (default after Application Reset) via bit CBS_OSTATE.WDTSUS if
it is not already stopped.
Table 3-18 OCDS Behavior of WDT
STCON. WDT_
STP SR.DS
0 X
1 1
1 0
1 0
1 0
1 0
3.8.5

Watchdog Timer Registers

3.8.5.1

Watchdog Timer Control Register 0

Register WDT_CON0 manages Password Access to the Watchdog Timer. It also stores
the timer reload value, a user-definable password field, a lock bit, and the End-of-
Initialization (ENDINIT) control bit.
User´s Manual
32-bit SCU, V1.18
to 8000 , the CPU is awakened and continues to execute
H H
CBS_OSTATE. CBS_OSTATE.
OEN SUS
X X
X X
0 X
1 0
1 1
1 1
System Control Unit (SCU)
CBS_MCDSSG.
SOS
X
X
X
X
0
1
3-139
TC1784
WDT
Action
Stopped
Stopped
Running
Stopped
Running
Stopped
V1.1, 2011-05