Contents Of The Segments - Infineon Technologies TC1784 User Manual

8.3

Contents of the Segments

This section summarizes the contents of the segments.
Segments 0-7
These segments are reserved segments in the TC1784.
Segment 8
From the SPB point of view (PCP), this memory segment allows accesses to all PMU
memories (PFLASH, DFLASH, EBU, BROM, TROM and OVRAM).
From the LMB point of view (CPU-PMI
MLI), this memory segment allows cached accesses to all PMU memories (PFLASH,
DFLASH, EBU, BROM, TROM and OVRAM).
Segment 9
This memory segment is reserved in the TC1784.
Segment 10
From the SPB point of view (PCP), this memory segment allows non-cached accesses
to all PMU memories (PFLASH, DFLASH, BROM, TROM and OVRAM).
From the LMB point of view (CPU-PMI, CPU-DMI, DMA including Cerberus and MLI),
this memory segment allows non-cached accesses to all PMU memories (PFLASH,
DFLASH, BROM, TROM and OVRAM).
From the DMA point of view, Move Engine, Cerberus and MLI accesses to this segment
are processed by the DMA LMB master interface on the LMB Bus.
Segment 11
This memory segment is reserved in the TC1784.
Segment 12
From the SPB point of view (PCP), this memory segment allows non-cached accesses
to the PMI scratch-pad RAM (SPRAM).
1) CPU access to OLDA address space via segment 8 (cached) results in LMB Bus Error Trap independent of
the PMU_OVRCON.OLDAEN bit setting.
2) For CPU accesses to segment 8 the specific PMI and DMI features for segment 8 accesses have to be taken
into account.
User´s Manual
MemMaps, V1.91
1)2) 1)2)
, CPU-DMI , DMA including Cerberus and
8-5
TC1784
Memory Maps
V1.1, 2011-05