Check Synchronising Mode; System Split Detector; Figure 4.3-2 Check Sync Function - Siemens 7SR224 Technical Manual

4.3.5

Check Synchronising Mode

The MOS On/Off input is provided to bypass the voltage and synchronising checks to provide an emergency
close function. Similarly, check synchronising can be overridden by the 79 OS On/Off input during autoreclose.
MOS On/Off can be set by binary inputs, Control commands and the function keys.
For the relay to issue a Check Sync Close the following conditions have to be met :
The Line and Bus voltages must both be considered live.
25 Check Sync Angle – the phase difference between the line and bus voltages has to be less than the phase
angle setting value. Whilst within the limits the phase angle can be increasing or decreasing and the element will
still issue a valid close signal.
25 Check Sync Slip Freq, [if enabled] – the frequency difference between line and bus has to be less than the slip
frequency setting value.
25 Check Sync Timer, [if enabled] – the phase angle and voltage blocking features have to be within their
parameters for the length of the slip timer setting. If either the phase angle or the voltage elements fall outside of
their limits the slip timer is reset. If they subsequently come back in then the slip timer has to time out before an
output is given. (This ensures that a close output will not be given if there is a transient disturbance on the system
due to e.g. some remote switching operations).
25 Line Undervolts, [if enabled] – the line voltage has to be above the line under-voltage setting value and also
above 5V for an output to be given.
25 Bus Undervolts, [if enabled] – the bus voltage has to be above the bus under-voltage setting value and also
above 5V for an output to be given.
25 Volt Differential, [if enabled] – the difference between the line and bus voltages has to be less than
the differential voltage detector setting value for an output to be given.
The synchronising is always started in the Check Synchronising mode of operation and the Check Synchronising
limits are applied. To proceed to System Synchronisation a system split must be detected as described in section
4.3.6
SLIP
Slip Within Range ?
Slip Frequency Setting
Φ
Angle
Phase Within Range ?
Phase Angle Setting
Line U/V
Block
Bus U/V
BLock
Δ
V Block
4.3.6

System Split Detector

A system split occurs where part of the system becomes islanded and operates separately. Under these
conditions the frequencies of the voltages either side of the breaker are asynchronous and therefore high phase
angle differences can occur as the voltage phasors slip past each other.
The decision to change to System Split settings, apply Close on Zero function, Lockout or ignore, during
autoreclose and manual closing is set separately by the 25 DAR Split Mode and 25 MC Split Mode settings. The
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&
Block
Block
Block
Figure 4.3-2 Check Sync Function
7SR224 Argus Description of Operation
Slip Timer &
Slip Timer
Setting
Chapter 1 Page 49 of 70
CheckSync
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