Figure 3.1-3 Logic Diagram: Time Delayed Overcurrent Element - Siemens 7SR224 Technical Manual

51-n Element
Enabled
AUTORECLOSE
Disabled
79 P/F Inst Trips
= 51-n
&
79 P/F Prot'n Trip n
= Delayed
Inhibit 51-n
51c
51-n Inrush
L1 81HBL2
Action
Off
Inhibit
L2 81HBL2
L3 81HBL2
51-n Dir Control
Non-Dir
Forward
Reverse
IL1 Fwd
IL1 Rev
IL2 Fwd
IL2 Rev
IL3 Fwd
IL3 Rev

Figure 3.1-3 Logic Diagram: Time Delayed Overcurrent Element

©2010 Siemens Protection Devices Limited
L1
See Voltage Controlled
L2
Overcurrent (51V)
L3
&
&
&
L1 Dir En
&
&
L2 Dir En
&
&
L3 Dir En
50/51
Measurement
IL1
IL2
IL3
51-n VTS Action
Off
Non Dir
Inhibit
VT Fail
&
1
&
&
1
&
&
1
&
7SR224 Argus Description of Operation
51-n Setting
51-n Charact
51-n Time Mult
51-n Delay (DTL)
51-n Min. Operate Time
51-n Follower DTL
51-n Reset
c
c
Pickup 1
trip
c
Pickup
trip
1
c
Pickup
trip
& &
&
&
&
General Pickup
51-n
1
L1 Dir En
1
L2 Dir En
1
L3 Dir En
Chapter 1 Page 21 of 70