Onkyo DV-CP702 Service Manual page 64

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
PORT ASSIGMENT-2
Class
CPU Circumference
function/ Digital Video
output/ CDDA input
CPU Debug
CPU external Bus I/F
Video DAC
Port name Function 1
I/O Description
PI02[5] I/O Port 25
PI02[6] I/O Port 26
PI02[7] I/O Port 27
PI03[1] I/O Port 31
PI03[2] I/O Port 32
PI03[3] I/O Port 33
PI03[4] I/O Port 34
PI03[5] I/O Port 35
PI03[6] I/O Port 36
PI03[7] I/O Port 37
PI04[0] I/O Port 40
PI04[1] I/O Port 41
PI04[2] I/O Port 42
PI04[3] I/O Port 43
PI04[4] I/O Port 44
PI04[5] I/O Port 45
PI04[6] I/O Port 46
PI04[7] I/O Port 47
SDITCK I SDI Clock input pin
SDITMS I SDI Access mode input pin
SDITDI I SDI Data input pin
SDITDO O SDI Data output pin
SDITRST I SDI Reset input pin
SDIDBI I SDI Interrupt Debugging
DAOUTB AO DAC Current output pin
PA0 AO DAC signal output pin
PA1 AO DAC signal output pin
PA2 AO DAC signal output pin
BIAS1 AI DAC Bias voltage (1)
BIAS2 AI DAC Bias voltage (2)
AVRI AI DAC Reference
voltage input pin
IREF AI DAC Reference
voltage input pin
DAOUT0B AO DAC Current
output pin
PA00 AO DAC signal output pin
PA01 AO DAC signal output pin
PA02 AO NC
BIAS01 AI DAC Bias voltage (1)
BIAS02 AI DAC Bias voltage (2)
AVRI0 AI DAC Reference
voltage input pin
IREF0 AI DAC Reference
voltage input pin
DV-CP702
Function 2 Function 3
I/O Descrition I/O Descrition
O BSEL2
O BSEL1
O HA10
I ADBCK
O OSDKEY I ADLRCK
I ADDIN
I ADMCK
O PXCLK
O HSYNC
O VSYNC
O PD[0]
O PD[1]
O PD[2]
O PD[3]
O PD[4]
O PD[5]
O PD[6]
O PD[7]