Onkyo DV-CP702 Service Manual page 60

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q2003 : IS24C08-3Z EEPROM
(8K-Bit 2-Wire Serial CMOS EEPROM)
PIN CONFIGURATION
A0 1
A1 2
A2 3
GND 4
FUNCTIONAL BLOCK DIAGRAM
Vcc
8
5
SDA
SCL
6
WP 7
SLAVE ADDRESS
REGISTER &
COMPARATOR
4
GND
nMOS
PIN DESCRIPTIONS
A0-A2
8 VCC
SDA
7 WP
SCL
6 SCL
WP
Vcc
5 SDA
GND
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and data
into and out of the device. The SDA pin is an open drain output and
can be wire-Ored with other open drain or open collector outputs.
The SDA bus requires a pullup resistor to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs.
The IS24C08 only use A2 input for hardwire addressing and a
total of two devices may be addressed on a single bus system.
The A0 and A1 pins are not used by IS24C08. They may be left
floating or tied to either GND or Vcc.
WP
WP is the Write Protect pin.
On the and 24C08, if the WP pin is tied to V
becomes Write Protected (Read only). On the 24C16,
if the WP pin is tied to Vcc the upper half array becomes Write
Protected (Read only). When WP is tied to GND or left
floating normal read/write operations are allowed to the
device.
CONTROL
LOGIC
WORD ADDRESS
COUNTER
ACK
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
EEPROM
ARRAY
Y
DECODER
Clock
DATA
DI/O
REGISTER
DV-CP702
the entire array
CC