Onkyo DV-CP702 Service Manual page 44

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q2601: BU2288FV CLOCK GENERATOR
PIN CONFIGURATION
1
VDD2
2
VSS2
3
CLK27M
4 TEST
5 AVDD
AVSS
6
7 XTALOUT
8 XTALIN
PIN FUNCTION
PIN No. PIN NAME
1 VDD2
2 VSS2
3 CLK27M
4 TEST
5 AVDD
6 AVSS
7 XTALOUT
8 XTALIN
9 CLKA
10 CLK512FS
11 DVSS
12 DVDD
13 CLK16M
14 FSEL1
15 CLK33M
16 OE
16
OE
15 33.8688MHz
CLK33M
FSEL1 14 L or NC (pull up)
CLK16M 13
16.9344MHz
DVDD 12
DVSS 11
CLK512FS 10 24.576 or 22.5792MHz
CLKA 9 16.9344 or 36.864MHz
FUNCTION
Digital VDD for 27MHz clock output
Digital GND for 27MHz clock output
27MHz clock output
Output for test
Analog VDD
Analog GND
Standard crystal output
Standard crystal input
Clock output (FSEL1=Open: 16.9344MHz, FEL1=36.864MHz)
Clock output (FSEL1=Open: 22.5792MHz, FEL1=24.576MHz)
Digital GND
Digital VDD
16.9344MHz clock output
Output select: with pull up
Open: 16.9344MHz (9pin), 22.5792MHz (10pin)
L: 36.864MHz (9pin), 24.576Mhz (10pin)
33.8688MHz clock output
Output enable (open: enable, L: disable): with pull up
DV-CP702