Onkyo DV-CP702 Service Manual page 62

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q2001 : M65783AFP (BACKEND DECODER)-1
Addres Bus/
Data Bus
Bus Control
Port/
CSIO
Port/
UART
Port/interrupt/ Timer/
BSEL/Addres
Port/ Bus Control/ CDDA input 2/
Digital display out/ SDI
Port/ Digital display out/
SDI
HA[11:14]: A11-A14
HAd[0:15]: A15-A30/D0-D15]
BSEL0
RS
WS
ALE
PIO0[0]: P00/Sin0
PIO0[1]: P01/Sout0
PIO0[2]: P02/Sclk0
PIO0[3]: P03/Srdy0
PIO0[4]: P04/Sin1
PIO0[5]: P05/Sout1
PIO0[6]: P06/Sclk1
PIO0[7]: P07/Srdy1
PIO1[0]: P10/Sin2
PIO1[1]: P11/Sout2
PIO1[2]: P12/Sclk2
PIO1[3]: P13/Srdy2
P1O1[4]: P14/RxD
P1O1[5]: P15/TxD
P1O1[6]: P16/CTS
P1O1[7]: P17/RTS
PIO2[0]: P20/INTM0
PIO2[1]: P21/INTM1
PIO2[2]: P22/INTM2/TMO0
PIO2[3]: P23/TMO1
PIO2[4]: P24/BSEL3/TMO2
PIO2[5]: P25/BSEL2
PIO2[6]: P26/BSEL1
PIO2[7]: P27/A10
PIO3[0]: P30/EXWIT
PIO3[1]: P31/ADBCK
PIO3[2]: P32/OSDKEY/ADLRCK
PIO3[3]: P33/ADDIN
PIO3[4]: P34/ADMCK/
SDITRSYNC
PIO3[5]: P35/PXCLK/SDITRCLK
PIO3[6]: P36/HSYNC/SDIEVENT[0]
PIO3[7]: P37/VSYNC/SDIEVENT[1]
PIO4[0]: P40/PD[0]/SDITRDATA[0]
PIO4[1]: P41/PD[1]/SDITRDATA[1]
PIO4[2]: P42/PD[2]/SDITRDATA[2]
PIO4[3]: P43/PD[3]/SDITRDATA[3]
PIO4[4]: P44/PD[4]/SDITRDATA[4]
PIO4[5]: P45/PD[5]/SDITRDATA[5]
PIO4[6]: P46/PD[6]/SDITRDATA[6]
PIO4[7]: P47/PD[7]/SDITRDATA[7]
MA[11:0]
MB[1:0]
DCS, DCS2
RAS
SDRAM
CAS
MCLK
DWE
DQMU, DQML
MD[15:0]
BD[7:0]
BCLK
Stream Data
BDEN
BDREQ
BSECH
CDMCK
CDBCK
CDDA Input 1
CDLRCK
CDDIN
CDDATA
AO0-AO2, AOD
DOCLK
Audio output
LRCLK
DACCLK
DOUT0, DOUT1
CLKO
CLKIN
ACLKI
Clock/ System
RESET
TEST[5:0]
NC1-4
PA0,PA1,PA2,
PA00,PA01,PA02
DAOUTB,DTOU0B Analog display out
AVRI,IREF,BIAS1,BIAS2,
AVRI0,IREF0,BIAS01,BIAS02
SDIYCK
SDITMS
SDITDI
SDI
SDITDO
SDITRST
SDIDBI
DV-CP702