Onkyo DV-CP702 Service Manual page 59

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q2303 : IC42S16400-7T SYNCHRONOUS DYNAMIC RAM
The IC42S16400 are high-speed 67, 108, 864-bit synchronous dynamic ramdam-access
memories, organized as 2,097, 152 x 8 x 4 and 1,48, 576 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock
frequency up to 133MHz for -7.
All input and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are
compatible with Low Voltage TTL.
PIN CONFIGURATIONS
V 1 54
DD
DQ0 2 53
V 3 52
DDQ
DQ1 4 51
DQ2 5 50
V 6 49
SSQ
DQ3 7 48
DQ4 8 47
V 9 46
DDQ
DQ5 10 45
DQ6 11 44
V 12 43
SSQ
DQ7 13 42
VDD 14 41
LDQM 15 40
WE 16 39
CAS 17 38
RAS 18 37
CS 19 36
BA0 20 35
BA1 21 34
A10 22 33
A0 23 32
A1 24 31
A2 25 30
A3 26 29
V 27 28
DD
PIN DESCRIPTIONS
V
SS
CLK
DQ15 CKE
CS
V
SSQ
RAS
DQ14
CAS
DQ13
WE
V DQ0 - DQ15
DDQ
DQ12
DQ11
V
SSQ
BLOCK DIAGRAM
DQ10
DQ9
CLK
Clock
V
DDQ
Generator
CKE
DQ8
V
SS
Address
NC
UDQM
CLK
CKE
NC
CS
A11
RAS
A9
CAS
A8
WE
A7
A6
A5
A4
V
SS
Master Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data I/O
Row
Address
Buffer
and
Mode
Refresh
Register
Counter
Column
Address
Buffer
and
Burst
Counter
DV-CP702
DQM DQ Mask Enable
A0 - 11 Address Input
BA0, 1 Bank Address
V Power Supply
DD
V Power Supply for DQ
DDQ
V Ground
SS
V Ground for DQ
SSQ
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ