Onkyo DV-CP702 Service Manual page 63

IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
PORT ASSIGMENT-1
Class
CPU outside Bus I/F
CPU Circumference
function
Port name Function 1
I/O Description
HA[11] O CPU Address
HA[12] O CPU Address
HA[13] O CPU Address
HA[14] O CPU Address
HA[0] I/O CPU Address/ Data
HAD[0] I/O CPU Address/ Data
HAD[1] I/O CPU Address/ Data
HAD[2] I/O CPU Address/ Data
HAD[3] I/O CPU Address/ Data
HAD[4] I/O CPU Address/ Data
HAD[5] I/O CPU Address/ Data
HAD[6] I/O CPU Address/ Data
HAD[7] I/O CPU Address/ Data
HAD[8] I/O CPU Address/ Data
HAD[9] I/O CPU Address/ Data
HAD[10] I/O CPU Address/ Data
HAD[11] I/O CPU Address/ Data
HAD[12] I/O CPU Address/ Data
HAD[13] I/O CPU Address/ Data
HAD[14] I/O CPU Address/ Data
HAD[15] I/O CPU Address/ Data
BSEL0 O Block select 0
RS O Read Strobe
WS O Wright Strobe
ALE O Address Latch Enable
PI03[0] I/O Port 30
PI00[0] I/O Port 00
PI00[1] I/O Port 01
PI00[2] I/O Port 02
PI00[3] I/O Port 03
PI00[4] I/O Port 04
PI00[5] I/O Port 05
PI00[6] I/O Port 06
PI00[7] I/O Port 07
PI01[0] I/O Port 10
PI01[1] I/O Port 11
PI01[2] I/O Port 12
PI01[3] I/O Port 13
PI01[4] I/O Port 14
PI01[5] I/O Port 15
PI01[6] I/O Port 16
PI01[7] I/O Port 17
PI02[0] I/O Port 20
PI02[1] I/O Port 21
PI02[2] I/O Port 22
PI02[3] I/O Port 23
PI02[4] I/O Port 24
PI02[5] I/O Port 25
PI02[6] I/O Port 26
PI02[7] I/O Port 27
DV-CP702
Function 2 Function 3
I/O Descrition I/O Descrition
I EXWIT
I Sin0
O Sout0
I/O Sclk0
I/O Srdy0
I Sin1
O Sout1
I/O Sclk1
I/O Srdy1
I Sin2
O Sout2
I/O Sclk2
I/O Srdy2
I RxD
O TxD
I CTS
O RTS
I INTM0
I INTM1
I INTM2 O TM00
O TM01
O BSEL3 O TM02
O BSEL2
O BSEL1
O HA10