Integrated Peripherals - FIC K7M-400A Instruction Manual

Memory Hole
When you install a Legacy ISA card, this feature allows you to select the
memory hole address range of the ISA cycle when the processor accesses
the selected address area. Please read your card manual for detail informa-
tion. When disabled, the memory hole at the (15-16MB) address will be
treated as a DRAM cycle when the processor accesses the15~16MB ad-
dress area. The options are: 15M - 16M, Disabled.
System BIOS Cacheable
When enabled, allows the ROM area F000H-FFFFH to be cacheable when
cache controller is activated. The options are: Enabled, Disabled.
Video RAM Cacheable
When enabled, allows the video RAM area to be cacheable.
The options are: Enabled, Disabled.

Integrated Peripherals

VIA OnChip IDE Device
OnChip SATA
This item allows you to diable the serial ATA controller embedded in South
Bridge. The options are: Auto, Disabled.
BIOS Setup
3 - 11