FIC K7M-400A Instruction Manual page 44

K7M-400A Mainboard Manual
AGP 3.0 Calibration cycle
This feature allows users to enable or disable AGP 3.0cablibration cycle.
The options are: Disabled, Enabled.
VGA Share Memory Size
It allows user to select the frame buffer size of VGA share memory.
The options are: Disabled, 16M, 32M, 64M.
CPU Direct Access FB
It allows user to enable or disable the direct access from CPU to frame
buffer of onboard video chip. The options are: Disabled, Enabled.
CPU & PCI Bus Control
PCI1/2 Master 0 WS Write
When enabled, allows a zero-wait-state-cycle delay when the PCI1/2 mas-
ter drive writes data to DRAM. The options are: Enabled, Disabled.
PCI1/2 Post Write
When enabled, allows the CPU to PCI1/2 master drive excutes post write.
The options are: Enabled, Disabled.AGP Master 1 WS Write
When enabled, the AGP bus master write access to DRAMs will add one
wait-state cycle. The options are: Enabled, Disabled.
VLink 8X Support
Enables VLink 8X support.
The options are: Enabled, Disabled.
PCI Delay Transaction
Enable this feature to abort the current PCI master cycle and to accept the
new PCI master request, it reaccepts the original PCI master and returns the
PCI data phase to the original PCI master.
The options are: Disabled, Enabled.
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