Advantech ECU-4784 Series User Manual page 79

PCI Express Root Port 3
This item allows users to enable or disable PCI Express Root Port.
ASPM Support
This item allows users to set the ASPM level. Force L0s- Force all links to
L0s state.
Auto-BIOS auto configure Disable- disables ASPM L1 Substates
This item allows users to change L1 Substates settings.
PME SCI
This item allows users to enable or disable PME SCI.
Hot Plug
This item allows users to enable or disable Hot Plug.
PCIe Speed
This item allows users to select PCIe Speed.
Detect Non-Compliance Device
This item allows users to enable or disable Detect Non-Compliance Device. If
enable, it will take more time at POST time.
Extra Bus Reserved
This item allows users to select Extra Bus Reserved (0~7) for bridges behind
this root bridge.
Reserved Memory
This item allows users to select Reserved Memory range for this root bridge.
Prefetchable Memory
This item allows users to select Prefetchable Memory range for this root
bridge.
Reserved I/O
This item allows users to select Reserved I/O (4k/8k/12k/16k.../48k) range
for this root bridge.
PCIE LTR
This item allows users to set the ASPM level. Force L0s- Force all links to
L0s state.
Auto-BIOS auto configure Disable- disables ASPM L1 Substates
This item allows users to enable or disable PCIE LTR.
PCIE LTR Lock
This item allows users to enable or disable PCIE LTR Configuration Lock.
Snoop Latency Ocerride
This item allows users to select Snoop Latency Ocerride for PCH PCIE.
Non Snoop Latency Ocerride
This item allows users to select Non Snoop Latency Ocerride for PCH PCIE.
69 ECU-4784 User Manual