Figure C.27Pci Express Root Port 3 Configuration - Advantech ECU-4784 Series User Manual

PCIe Speed
This item allows users to select PCIe Speed.
Detect Non-Compliance Device
This item allows users to enable or disable Detect Non-Compliance Device. If
enable, it will take more time at POST time.
Extra Bus Reserved
This item allows users to select Extra Bus Reserved (0~7) for bridges behind
this root bridge.
Reserved Memory
This item allows users to select Reserved Memory range for this root bridge.
Prefetchable Memory
This item allows users to select Prefetchable Memory range for this root
bridge.
Reserved I/O
This item allows users to select Reserved I/O (4k/8k/12k/16k.../48k) range
for this root bridge.
PCIE LTR
This item allows users to enable or disable PCIE LTR.
PCIE LTR Lock
This item allows users to enable or disable PCIE LTR Configuration Lock.
Snoop Latency Ocerride
This item allows users to select Snoop Latency Ocerride for PCH PCIE.
Non Snoop Latency Ocerride
This item allows users to select Non Snoop Latency Ocerride for PCH PCIE.
– PCI Express Root Port 3 Configuration
Figure C.27 PCI Express Root Port 3 Configuration
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