Figure C.24Pci Express Configuration - Advantech ECU-4784 Series User Manual

 PCI Express Configuration
Figure C.24 PCI Express Configuration
– PCI Express Clock Gating
This item allows users to enable or disable PCI Express Clock Gating for
each root port.
– DMI Link ASPM Control
This item allows users to enable or disable DMI Link ASPM Control.
The Control of Active State Power Management on both NB side and SB side
of the DMI Link.
– DMI Link Extended Synch Control
This item allows users to enable or disable DMI Link Extended Synch Con-
trol.
The Control of Extended Synch on SB side of the DMI Link.
– PCIe-USB Glitch W/A
This item allows users to enable or disable PCIe-USB Glitch W/A.
PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG
Port.
– Subtractive Decode
This item allows users to enable or disable Subtractive Decode.
– PCI Express Root Port 1
This item allows users to change PCI Express Root Port 1 settings.
– PCI Express Root Port 2
This item allows users to change PCI Express Root Port 2 settings.
– PCI Express Root Port 3
This item allows users to change PCI Express Root Port 3 settings.
– PCI Express Root Port 4
This item allows users to change PCI Express Root Port 4 settings.
65 ECU-4784 User Manual