Supermicro X10DRH-CLN4 User Manual page 98

X10DRH-CLN4/iLN4 Motherboard User's Manual
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Recovery Firmware Version
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ME Firmware Features
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ME Firmware Status #1
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ME Firmware Status #2
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Current State
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Error Code
Altitude
This item indicates the altitude of this machine that is above the sea level. The
value is shown in meters. If the value is unknown, enter the number "80000000".
MCTP (Management Component Transport Protocol) Bus Owner
This item indicates the location of the MCTP Bus owner. Enter 0's to all fields to
disable the MCTP Bus owner.
 PCIe/PCI/PnP Configuration
PCI Latency Timer
Use this item to configure the PCI latency timer for a device installed on a PCI bus.
Select 32 to set the PCI latency timer to 32 PCI clock cycles. The options are 32,
64, 96, 128, 160, 192, 224, and 248 (PCI Bus Clocks).
PERR# Generation
Select Enabled to allow a PCI device to generate a PERR (PCI/PCI-E Parity Error)
number for a PCI bus error event. The options are Enabled and Disabled.
SERR# Generation
Select Enabled to allow a PCI device to generate an SERR (System Error) number
for a PCI bus error event. The options are Enabled and Disabled.
PCI PERR/SERR Support
Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)
runtime error reporting for a PCI/PCI-E slot. The options are Enabled and Disabled.
Above 4G Decoding (Available if the system supports 64-bit PCI decoding)
Select Enabled to decode a PCI device that supports 64-bit in the space above 4G
Address. The options are Enabled and Disabled.
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