Intel BX80623G530 Specification page 50

BJ97. Programming PDIR And an Additional Precise PerfMon Event May
Cause Unexpected PMI or PEBS Events
Problem: PDIR (Precise Distribution for Instructions Retired) mechanism is activated by
programming INST_RETIRED.ALL (event C0H, umask value 00H) on Counter 1. When
PDIR is activated in PEBS (Precise Event Based Sampling) mode with an additional
precise PerfMon event, an incorrect PMI or PEBS event may occur.
Implication: Due to this erratum, when another PEBS event is programmed along with PDIR, an
incorrect PMI or PEBS event may occur.
Workaround: Software should not program another PEBS event in conjunction with the PDIR
mechanism.
Status: For the steppings affected, see the Summary Tables of Changes.
BJ98. Performance Monitoring May Overcount Some Events During
Debugging
Problem: If the debug-control register (DR7) is configured so that some but not all of the
breakpoints in the debug-address registers (DR0-DR3) are enabled and one or more of
the following performance-monitoring counters are locally enabled (via
IA32_CR_PERMON_EVNTSEL_CNTR{3:0}):

BR_INST_RETIRED
BR_MISP_RETIRED
FP_ASSIST
FP_ASSIST
INST_RETIRED
MACHINE_CLEARS
MEM_LOAD_UOPS_LLC_HIT_RETIRED
MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS
MEM_LOAD_UOPS_RETIRED
MEM_TRANS_RETIRED
MEM_UOPS_RETIRED
OTHER_ASSISTS
ROB_MISC_EVENTS.LBR_INSERTS
UOPS_RETIRED

Any of the globally enabled (via IA32_CR_EMON_PERF_GLOBAL_CTRL) counters may
overcount certain events when a disabled breakpoint condition is met
Implication: Performance-monitor counters may indicate a number greater than the number of
events that occurred.
Workaround: Software can disable all breakpoints by clearing DR7. Alternatively, software can ensure
that, for a breakpoint disabled in DR7, the corresponding debug-address register
contains an address that prevents the breakpoint condition from being met (e.g., a
non-canonical address).
Status: For the steppings affected, see the Summary Tables of Changes.
BJ99. LTR Message is Not Treated as an Unsupported Request
Problem: The PCIe* root port does not support LTR (Latency Tolerance Reporting) capability.
However, a received LTR message is not treated as a UR (Unsupported Request).
Implication: Due to this erratum, an LTR message does not generate a UR error.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
50 Specification Update