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BJ47.
Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication:
If this erratum occurs, the system may have unpredictable behavior, including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the Intel 64 and IA-32 Intel
Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
Intel has not observed this erratum with any commercially available software or
system.
Workaround:
Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ48.
PCI Express* Graphics Receiver Error Reported When Receiver With
L0s Enabled and Link Retrain Performed
Problem:
If the Processor PCI Express* root port is the receiver with L0s enabled and the root
port itself initiates a transition to the recovery state via the retrain link configuration bit
in the 'Link Control' register (Bus 0; Device 1; Functions 0, 1, 2 and Device 6; Function
0; Offset B0H; bit 5), then the root port may not mask the receiver or bad DLLP (Data
Link Layer Packet) errors as expected. These correctable errors should only be
considered valid during PCIe configuration and L0 but not L0s. This causes the
processor to falsely report correctable errors in the 'Device Status' register (Bus 0;
Device 1; Functions 0, 1, 2 and Device 6; Function 0; Offset AAH; bit 0) upon receiving
the first FTS (Fast Training Sequence) when exiting Receiver L0s. Under normal
conditions there is no reason for the Root Port to initiate a transition to Recovery. Note:
This issue is only exposed when a recovery event is initiated by the processor.
Implication:
The processor does not comply with the PCI Express 2.0 Specification. This does not
impact functional compatibility or interoperability with other PCIe devices.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BJ49.
Unexpected #UD on VZEROALL/VZEROUPPER
Problem:
Execution of the VZEROALL or VZEROUPPER instructions in 64-bit mode with VEX.W set
to 1 may erroneously cause a #UD (invalid-opcode exception).
Implication:
The affected instructions may produce unexpected invalid-opcode exceptions in 64-bit
mode.
Workaround:
Compilers should encode VEX.W = 0 for executions of the VZEROALL and VZEROUPPER
instructions in 64-bit mode to ensure future compatibility.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
®
Architecture
35
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