Intel BX80623G530 Specification page 13

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Errata (Sheet 4 of 5)
Steppings
Number
D-2 Q-0
BJ83 X X
X X
BJ84
BJ85 X X
BJ86 X X
BJ87 X X
X X
BJ88
BJ89 X X
BJ90 X X
BJ91 X X
BJ92 X X
BJ93 X X
BJ94 X X
BJ95 X x
BJ96 X X
BJ97 X X
BJ98 X X
BJ99 X X
BJ100 X X
BJ101 X X
BJ102 X X
BJ103 X X
BJ104 X X
BJ105 X X
BJ106 X
BJ107 X
BJ108 X
BJ109 X
X X
BJ110
Specification Update
Status
No Fix PCIe* Presence Detect State May Not be Accurate After a Warm Reset
Display Corruption May be Seen After Graphics Voltage Rail (VCC_AXG) Power
No Fix
Up
PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate
No Fix
with 32-bit Length Registers
VM Entries That Return From SMM Using VMLAUNCH May Not Update The
No Fix
Launch State of the VMCS
No Fix Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered
An Unexpected Page Fault May Occur Following the Unmapping and Re-mapping
No Fix
of a Page
A PCIe* Device That Initially Transmits Minimal Posted Data Credits May Cause a
No Fix
System Hang
No Fix Some Model Specific Branch Events May Overcount
Some Performance Monitoring Events in AnyThread Mode May Get Incorrect
No Fix
Count
No Fix PDIR May Not Function Properly With FREEZE_PERFMON_ON_PMI
For A Single Logical Processor Package, HTT May be Set to Zero Even Though
No Fix
The Package Reserves More Than One APIC ID
No Fix LBR May Contain Incorrect Information When Using FREEZE_LBRS_ON_PMI
No Fix A First Level Data Cache Parity Error May Result in Unexpected Behavior
No Fix Intel® Trusted Execution Technology ACM Revocation
Programming PDIR And an Additional Precise PerfMon Event May Cause
Plan Fix
Unexpected PMI or PEBS Events
No Fix Performance Monitoring May Overcount Some Events During Debugging
No Fix LTR Message is Not Treated as an Unsupported Request
Use of VMASKMOV to Access Memory Mapped I/O or Uncached Memory May
No Fix
Cause The Logical Processor to Hang
No Fix PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full
No Fix XSAVEOPT May Fail to Save Some State after Transitions Into or Out of STM
Performance Monitor Precise Instruction Retired Event May Present Wrong
No Fix
Indications
The Value in IA32_MC3_ADDR MSR May Not be Accurate When MCACOD 0119H
No Fix
is Reported in IA32_MC3_Status
No Fix MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate
No Fix Enabling/Disabling PEBS May Result in Unpredictable System Behavior
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for
No Fix
VEX.vvvv May Produce a #NM Exception
No Fix Unexpected #UD on VZEROALL/VZEROUPPER
No Fix Successive Fixed Counter Overflows May be Discarded
Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM
No Fix
Exception
ERRATA
13